参数资料
型号: 71M6531F-DB
厂商: Maxim Integrated Products
文件页数: 80/121页
文件大小: 0K
描述: BOARD DEMO 71M6531F
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: 71M6531
主要属性: 单相功率表
已供物品: 2 个板,线缆,CD,电源
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Name
FLSH_ERASE
[7:0]
Location
SFR 94[7:0]
Reset
0
Wake
0
Dir
W
Description
Flash Erase Initiate. (Default = 0x00) . FLSH_ERASE is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[5:0] @ SFR 0xB7.
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE will have no effect. The erase cycle is not
completed until 0x00 is written to FLSH_ERASE .
Mass Erase Enable.
FLSH_MEEN
SFR B2[1]
0
0
W
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Flash Page Erase Address. (Default = 0x00)
FLSH_PGADR
[5:0]
SFR B7 [7:2]
0
0
W
FLSH_PGADR [5:0] with FL_BANK [2:0], sets the Flash Page Address (page 0 through
127) that will be erased during the Page Erase cycle.
Must be re-written for each new Page Erase cycle.
FLSH_PWE
GP0
GP7
IE_FWCOL0
IE_FWCOL1
IE_PB
IE_PLLRISE
IE_PLLFALL
IEN_SPI
SFR B2[0]
20C0
20C7
SFR E8[2]
SFR E8[3]
SFR E8[4]
SFR E8[6]
SFR E8[7]
20B0[4]
0
0
0
0
0
0
0
0
0
0
NV
NV
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Write Enable. This bit must be cleared by the MPU after each byte write op-
eration. Write operations to this bit are inhibited when interrupts are enabled.
0 = MOVX commands refer to XRAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
Non-volatile general-purpose registers powered by the RTC supply. These registers
maintain their value in all power modes, but will be cleared on reset. The values of
GP0…GP7 will be undefined if VBAT drops below the minimum value.
Interrupt flags for Firmware Collision Interrupt. See the Flash Memory section for
details.
PB flag. Indicates that a rising edge occurred on PB. Firmware must write a zero to
this bit to clear it. The bit is also cleared when the MPU requests SLEEP or LCD
mode. On bootup, the MPU can read this bit to determine if the part was woken with
the PB (DIO0[0]).
Indicates that the MPU was woken or interrupted (INT4) by system power becoming
available, or more precisely, by PLL_OK rising. The firmware must write a zero to this
bit to clear it.
Indicates that the MPU has entered BROWNOUT mode because system power has
become unavailable (INT4), or more precisely, because PLL_OK fell. This bit will not
be set if the part wakes into BROWNOUT mode because of PB or the WAKE timer.
The firmware must write a zero to this bit to clear it.
SPI interrupt enable.
80
Rev 2
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