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参数资料
| 型号： | 73S1210F-68IMR/F/P |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 101/126页 |
| 文件大小： | 0K |
| 描述： | IC SMART CARD READER PROG 68-QFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | 73S12xx |
| 核心处理器： | 80515 |
| 芯体尺寸： | 8-位 |
| 速度： | 24MHz |
| 连通性： | I²C，智能卡，UART/USART |
| 外围设备： | LED，POR，WDT |
| 输入/输出数： | 8 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 6.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 68-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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73S1210F Data Sheet
DS_1210F_001
76
Rev. 1.4
Special Notes Regarding Synchronous Mode Operation
When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card
interface operates in synchronous mode and there are changes in the definition and behavior of pertinent
register bits and associated circuitry. The following requirements are to be noted:
1.
The source for the smart card clock (CLK or SCLK) is the ETU counter. Only the actively selected
interface can have a running synchronous clock. In contrast, an unselected interface may have a
running clock in the asynchronous mode of operation.
2.
The control bits CLKLVL, SCLKLVL, CLKOFF, and SCLKOFF are functional in synchronous mode.
When the CLKOFF bit is set, it will not truncate either the logic low or logic high period when the (stop
at) level is of opposite polarity. The CLK/SCLK signal will complete a correct logic low or logic high
duty cycle before stopping at the selected level. The CLK “start” is a result of the falling edge of the
CLKOFF bit. Setting clock to run when it is stopped low will result in a half period of low before going
high. Setting clock to run when it is stopped high will result in the clock going low immediately and
then running at the selected rate with 50% duty cycle (within the limitations of the ETU divisor value).
3.
The Rlen(7:0) is configured to count the falling edges of the ETU clock (CLK or SCLK) after it has
been loaded with a value from 1 to 255. A value of 0 disables the counting function and RLen
functions such as I/O source selection (I/O signal bypasses the FIFOs and is controlled by the
SCCLK/SCECLK SFRs). When the RLen counter reaches the “max” (loaded) value, it sets the
order to start the counting/clocking process again. This allows the processor to select the number of
CLK cycles and hence, the number of bits to be read or written to/from the card.
4.
The FIFO is not clocked by the first CLK (falling) edge resulting from a CLKOFF de-assertion (a clock
start event) when the CLK was stopped in the high state and RLen has been loaded but not yet
clocked.
5.
The state of the pin IO or SIO is sampled on the rising edge of CLK/SCLK and stored in bit 5 of the
6.
When Rlen = max or 0 and I2CMODE= 1 (STXCtl, b7), the IO or SIO signal is directly controlled by the
data and direction bits in the respective SCCtl and SCECtl register. The state of the data in the TX
FIFO is bypassed.
7.
In the SPrtcol register, bit 6 (MODE9/8B) becomes active. When set, the RXData FIFO will read
nine-bit words with the state of the ninth bit being readable in SRXCtl, bit 7 (B9DAT). The RXDAV
interrupt will occur when the ninth bit has been clocked in (rising edge of CLK or SCLK).
8.
Care must be taken to clear the RX and TX FIFOs at the start of any transaction. The user shall read
the RX FIFO until it indicates empty status. Reading the TX FIFO twice will reset the input byte
pointer and the next write to the TX FIFO will load the byte to the “first out” position. Note that the bit
pointer (serializer/deserializer) is reset to bit 0 on any change of the TX/RXD bit.
Special bits that are only active for sync mode include: SRXCtl, b7 “BIT9DAT”, SPrtcol, b6 “MODE9/8B”,
STXCtl, b7 “I2CMODE”, and the definition of SCInt, b7, which was “WAITTO”, becomes RLenINT interrupt,
and SCIE, b7, which was “WTOIEN”, becomes RLenIEN.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 73S1210F-68M/F/PB | 制造商:Maxim Integrated Products 功能描述:- Trays |
| 73S1210F-68M/F/PG | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| 73S1210F-68M/F/PH | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| 73S1210F-68M/F/PJ | 制造商:Maxim Integrated Products 功能描述:SCR+PPAD/SRL INTFC/PWR MGT-3.11CODE - Rail/Tube |
| 73S1210F-68MR/F/PG | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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