参数资料
型号: 73S1210F-68IMR/F/P
厂商: Maxim Integrated Products
文件页数: 111/126页
文件大小: 0K
描述: IC SMART CARD READER PROG 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: 73S12xx
核心处理器: 80515
芯体尺寸: 8-位
速度: 24MHz
连通性: I²C,智能卡,UART/USART
外围设备: LED,POR,WDT
输入/输出数: 8
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 68-VFQFN 裸露焊盘
包装: 带卷 (TR)
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
85
Card Status/Control Register (CRDCtl): 0xFE05
0x00
This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This
register must be written to properly configure Debounce, Detect_Polarity (= 0 or = 1), and the pull-
up/down enable before setting CDETEN. The card detect logic is functional even without smart card logic
clock. When the PWRDN bit is set = 1, no debounce is provided but card presence is operable.
Table 77: The CRDCtl Register
MSB
LSB
DEBOUN
CDETEN
DETPOL
PUENB
PDEN
CARDIN
Bit
Symbol
Function
CRDCtl.7
DEBOUN
Debounce - When set = 1, this will enable hardware debounce of
the card detect pin. The debounce function shall wait for 64ms of
stable card detect assertion before setting the CARDIN bit. This
counter/timer uses the keypad clock as a source of 1kHz signal.
De-assertion of the CARDIN bit is immediate upon de-assertion
of the card detect pin(s).
CRDCtl.6
CDETEN
Card Detect Enable - When set = 1, activates card detection
input. Default upon power-on reset is 0.
CRDCtl.5
CRDCtl.4
CRDCtl.3
DETPOL
Detect Polarity - When set = 1, the DETCARD pin shall interpret
a logic 1 as card present.
CRDCtl.2
PUENB
Enable pull-up current on DETCARD pin (active low).
CRDCtl.1
PDEN
Enable pull-down current on DETCARD pin.
CRDCtl.0
CARDIN
Card Inserted - (Read only). 1 = card inserted, 0 = card not
inserted. A change in the value of this bit is a “card event.” A
read of this bit indicates whether smart card is inserted or not
inserted in conjunction with the DETPOL setting.
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