参数资料
型号: 73S1210F-68IMR/F/P
厂商: Maxim Integrated Products
文件页数: 85/126页
文件大小: 0K
描述: IC SMART CARD READER PROG 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: 73S12xx
核心处理器: 80515
芯体尺寸: 8-位
速度: 24MHz
连通性: I²C,智能卡,UART/USART
外围设备: LED,POR,WDT
输入/输出数: 8
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 68-VFQFN 裸露焊盘
包装: 带卷 (TR)
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
61
1.7.13 Keypad Interface
The 73S1210F supports a 30-button (6 rows x 5 columns) keypad (SPST Mechanical Contact Switches)
interface using 11 dedicated I/O pins. Figure 12 shows a simplified block diagram of the keypad
interface.
Scan
p
u
ll-
u
p
Debouncing
D
e
b
o
u
n
c
e
T
im
e
7
6
5
4
3
2
1
0
KSIZE Register
6
(1) KCOL is normally used as Read only
register. When hardware keyscan mode
is disabled, this register is to be used by
firmware to write the column data to
handle firmware scanning.
K
e
y
_
D
e
te
c
t
Hardware Scan Enable
6
C
o
lu
m
n
S
c
a
n
O
rd
e
r
5
Column Value
Row Value
K
e
y
_
D
e
te
c
t_
E
n
a
b
le
KORDERL / H Registers
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
KCOL Register
(1)
7
6
5
4
3
2
1
0
KROW Register
Dividers
1kHz
S
c
a
n
T
im
e
KSCAN Register
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
KSTAT Register
Keypad Clock
VDD
p
u
ll-
u
p
COL4:0
R
O
W
5
:0
73S1210F
If smaller keypad than 6 x 5 is to be
implemented, unused row inputs
should be connected to VDD. Unused
column outputs should be left
unconnected.
VDD
Figure 12: Simplified Keypad Block Diagram
There are five drive lines (outputs) corresponding to columns and 6 sense lines (inputs) corresponding to
rows. Hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external
resistors in the keypad. Key scanning happens by asserting one of the 5 column lines low and looking for
a low on a sense line indicating that a key is pressed (switch closed) at the intersection of the drive/sense
(column/row) line in the keypad. Key detection is performed by hardware with an incorporated debounce
timer. Debouncing time is adjustable through the KSCAN register. Internal hardware circuitry performs
column scanning at an adjustable scanning rate and column scanning order through registers KSCAN
and KORDERL / KORDERH. Key scanning is disabled at reset and must be enabled by firmware. When
a valid key is detected, an interrupt is generated and the valid value of the pressed key is automatically
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