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参数资料
| 型号： | 7805ALPRPDB |
| 厂商： | MAXWELL TECHNOLOGIES |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 |
| 封装： | RAD-PAK, DIP-28 |
| 文件页数： | 11/34页 |
| 文件大小： | 605K |
| 代理商： | 7805ALPRPDB |
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Memory
PRELIMINARY
19
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
TABLE 19. VBIAS SELECTION TABLE
Main DAC or Sub DAC Selection
MAIN/SUB
0
Writing a 0 to this bit means that the data in the next data register write is transferred to the selected Main
DAC.
1
Writing a 1 to this bit means that the data in the next data register write is transferred to the selected Sub
DAC.
This applies to the 10-bit parallel load feature. In byte load mode, (Figure 15) DB0 selects the Main or Sub
DAC data registers.
Standby
STBY
0
Places the selected DAC and its associated linear circuitry in Standby Mode.
1
Normal operation (default on power-up).
Clear
CLR
0
Normal operation.
1
Clears the output of the selected Main DAC to one of two conditions depending on the input coding selected.
With offset binary coding the Main DAC output is cleared to the bottom of the transfer function, VBIAS/16 and
with twos complement coding the Main DAC output is cleared to midscale VBIAS. The Sub DAC is unaffected
by a clear operation. An LDAC signal has to be applied to the DAC for a channel clear to be implemented.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 7805ALPRPDE | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:16-Bit Latchup Protected ADC |
| 7805ALPRPDH | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:16-Bit Latchup Protected ADC |
| 7805ALPRPDI | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:16-Bit Latchup Protected ADC |
| 7805ALPRPDK | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:16-Bit Latchup Protected ADC |
| 7805ALPRPFE | 制造商:MAXWELL 制造商全称:Maxwell Technologies 功能描述:16-Bit Latchup Protected ADC |
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