参数资料
型号: 7805ALPRPDB
厂商: MAXWELL TECHNOLOGIES
元件分类: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28
封装: RAD-PAK, DIP-28
文件页数: 14/34页
文件大小: 605K
代理商: 7805ALPRPDB
Memory
PRELIMINARY
21
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
FIGURE 18. FLOWCHART FOR CONTROLLING THE 7805ALP
DACs in 10-Bit Parallel Mode Following Power-Up mode as the selection can be made using the hardware bit DB0
and this will reduce the software overheads when accessing the DACs.
CLEAR FUNCTIONS
There are three methods of clearing the output of the Main DAC in these devices. The first is the external hardware
clear. An active low logic signal applied to this pin clears all the DACs in the package. The voltage to which the output
is cleared will depend on the input coding selected. The Main DAC outputs are cleared to midscale (VBIAS) in twos
complement format and to the bottom of the transfer function (VBIAS/16) in offset binary format. The second way of
clearing the main DACs is a software clear by asserting the SCLR bit in the system control register of the part. Writing
a one to this bit clears all DACs in the package. The third method of clearing a DAC is to write a one to the CLR bit in
the channel control register. This differs from that of the system control register in that only the selected DACs output
is cleared. The channel clear requires an LDAC pulse to activate it.
There is only one way of clearing the output of the Sub DAC and that is to use the external hardware clear. The output
of the Sub DAC is cleared to midscale (0 V) regardless of the input coding being used. Figure 19 shows a simplified
diagram of the implementation of the clear functions for a single DAC in the package.
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