参数资料
型号: 7805ALPRPDB
厂商: MAXWELL TECHNOLOGIES
元件分类: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28
封装: RAD-PAK, DIP-28
文件页数: 8/34页
文件大小: 605K
代理商: 7805ALPRPDB
Memory
PRELIMINARY
16
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
FIGURE 14. 7805ALP MAIN DAC DATA REGISTER CONFIGURATION (MODE = 1, 10 /8 = 1, MAIN/SUB = 0))
Figure 15 shows the bit allocations for writing to the Sub DAC.
FIGURE 15. 7805ALP SUB DAC DATA REGISTER CONFIGURATION (MODE = 1, MAIN /SUB = 1)
Each DAC has a separate channel control register. The following is a brief discussion on the bits in each of the control
registers.
DAC Selection (A2, A1, A0)
The external address pins in conjunction with CS, WR and MODE are used to address the various DAC data and con-
trol registers. Table 18 shows how these DAC registers can be addressed on the 7805ALP. Refer to Figures 11 to 15
for information on the registers.
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