参数资料
型号: 7805ALPRPDB
厂商: MAXWELL TECHNOLOGIES
元件分类: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28
封装: RAD-PAK, DIP-28
文件页数: 19/34页
文件大小: 605K
代理商: 7805ALPRPDB
Memory
PRELIMINARY
26
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
Configuring the 7805ALP for Twos Complement Coding
Figure 23 shows a typical configuration for the 7805ALP. The circuit can be used for either 3.3 V or 5 V operation and
uses the internal VDD/2 as the reference for the part and 10-bit parallel interfacing is used. The following are the steps
required to operate the Main DACs in this part.
FIGURE 23. TYPICAL CONFIGURATION FOR 7805ALP
System Control Register Write:
MODE = 0, address inputs (A2, A1, A0) are don’t cares.
Write 020 Hex
Configure part for 10-bit parallel, twos complement coding, normal operation Channel
Control Register Write:
MODE = 0, address inputs (A2, A1, A0) select desired channel.
Write 011 Hex
Internal VDD/2 selected as VBIAS for DAC, and any DAC data writes that follow are to
the Main DAC.
DAC Data Register Write:
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