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参数资料
型号： A29DL324SERIES
英文描述： 32M-Bit CMOS Low Voltage Dual Operation Flash Memory 4M-Byte by 8-Bit (Byte Mode) / 2M-Word by 16-Bit
中文描述： 32兆位的CMOS低电压双操作闪存分字节由8位（字节模式）/ 200万词由16位
文件页数： 6/46页
文件大小： 467K
代理商： A29DL324SERIES
A29DL323 Series
PRELIMINARY (May, 2002, Version 0.0)
6
AMIC Technology, Inc.
Read Operation
The read operation is controlled by the
OE
and /OE. The
/CE is used to select a device, and the
OE
controls data
output. The following three access times are used
depending on the condition.
-
Address access time (t
ACC
): Time until valid data is
output after an address has been determined
(however, after
CE
).
-
CE
access time (t
CE)
: Time until valid data is output
after
CE
has been determined (however, after
address).
-
OE
access time (t
OE
): Time until valid data is output
after
OE
has been determined (however,
OE
must
be input after t
ACC
-t
OE
, t
CE
-t
OE
after address and
CE
have been determined).
On power-up, the device is automatically set in the read
mode. To read the device without changing address
immediately after power application, either execute
hardware reset or briefly lower
CE
to V
IL
from V
IH
.
For the timing waveform, refer to Timing Waveform for
Read Cycle (1).
Write Operation
The operation of the device is controlled by writing
commands to the registers. The command register is a
function that latches the address and data necessary for
executing an instruction and does not occupy the memory
area.
If an illegal address or data is written or if an address or
data is written in the wrong sequence, the device is reset to
the read mode.
Standby Mode
The standby mode is set when V
IH
is input to the
CE
. The
current consumption in the standby mode can be lowered to
5
μ
A or less in two ways.
One is to use
CE
and
RESET
. Input VCC
±
0.3 V to
CE
and
RESET
. However, while automatic programming or
erasing is being executed, the operating supply current
(I
CC2
) does not decrease to 5
μ
A or lower even if
CE
= V
IH
.
If a read operation is executed in the standby mode, data is
output at
CE
access time.
The other is to input GND
±
0.3 V to the
RESET
. At this
time, the level of
CE
is V
IH
or V
IL
. In this case, t
RH
is
required for the device to return to the read mode from the
standby mode.
For the timing waveform, refer to Timing Waveform for
Read Cycle (2).
Hardware Reset Pin
The device is reset to the read mode if V
IL
is input to the
RESET
for the duration of t
RP
and V
IH
for the duration of
t
RH
. While V
IL
is being input to the
RESET
, all commands
are ignored, and the output pins go into a Hi-Z state. If the
voltage on
RESET
is kept to GND
±
0.2 V at this time, the
current consumption can be lowered to 5
μ
A or less. If V
IH
is
input to the
RESET
, t
READY
is required until data is output.
For the timing waveform, refer to Timing Waveform for
Read Cycle (2).
Output Disable Mode
Output from the device is disabled (Hi-Z state) if V
IH
is input
to the
OE
.
Sector Group Protection
Protect the sector group by using a command.
OE
or
WE
control is no need.
Temporary Sector Group Unprotect
Protection of a sector group can be temporarily canceled.
When V
ID
is input to
RESET
, the temporary sector group
unprotect mode is set. If a protected sector is selected in
this mode, it can be programmed or erased. If the mode is
canceled, the sector group is protected again.
For the timing waveform, refer to Timing Waveform for
Temporary Sector Group Unprotect.
Product ID
Read the product ID code by using a command.
Automatic Sleep Mode
The automatic sleep mode is used to reduce the power
consumption substantially during a read operation.
If an address is held longer than the minimum read
cycle time (t
RC
), the sleep mode (low power
consumption
mode) is automatically set. In this mode, the
output data is latched and continuously output.
In the automatic sleep mode,
CE
,
WE
, and
OE
do not
have to be controlled. At this time, the current consumption
decreases to 5
μ
A or less. During dual operation,
however, the current consumption is power supply
current (I
CC6
, I
CC7
).
If the address is changed, the automatic sleep mode
is canceled automatically, the device returns to the
read mode, and the data of the newly input address is
output.
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相关代理商/技术参数
参数描述
A29DL324TG-120 制造商:AMICC 制造商全称:AMIC Technology 功能描述:32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
A29DL324TG-70 制造商:AMICC 制造商全称:AMIC Technology 功能描述:32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
A29DL324TG-80 制造商:AMICC 制造商全称:AMIC Technology 功能描述:32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
A29DL324TG-90 制造商:AMICC 制造商全称:AMIC Technology 功能描述:32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
A29DL324TV-120 制造商:AMICC 制造商全称:AMIC Technology 功能描述:32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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