参数资料
型号: A3944KLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 12/31页
文件大小: 0K
描述: IC PREDRIVER MOSFET 6CH TSSOP
标准包装: 8,000
配置: 低端
输入类型: 并行/串行
延迟时间: 200ns
电流 - 峰: 50mA
配置数: 6
输出数: 6
电源电压: 6 V ~ 40 V
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 带卷 (TR)
A3944
Automotive, Low Side FET Pre-Driver
terminal. The voltage output capability of the current sources is
limited such that they cannot source current when the output volt-
age is greater than V OCL or sink current when the output voltage
is less than V OCL . The equivalent circuit is shown in figure 4a.
The typical sink and source currents are shown graphically in
figure 4b.
When a channel is in the off-state the current generators source or
sink current through the DRNx terminal in an attempt to pull the
voltage at the terminal to the open load clamp voltage, V OCL . The
resulting voltage at the DRNx terminal, V DRNx , is measured to
test for a short to ground or an open load.
Normal Operation
If a load is present, the load supply is active, and there are no
shorts to ground, then the load will pull V DRNx above V OCL .
I DPD
V DRNx will then be greater than the open load threshold, V OL ,
and no fault is detected (see figure 3). If the NPD bit is zero then
the current sink will pull I DPD from the supply through the load,
through the DRNx terminal, to V OCL
The open load threshold, V OL , and the open load clamp voltage,
V OCL , are a both a fixed percentage of the voltage at the VREG
terminal and are common to all channels.
Short to Ground
If a short to ground is present, then V DRNx will be pulled low by
the short circuit. V DRNx will be less than the short detect thresh-
old, V STG , and a short to ground fault is reported (see figure 3).
The short detect threshold voltage, V STG , is selected, per channel,
as a percentage of the voltage at the VREG terminal. The voltage
selection is determined by the SG bit (bit 0 of the fault configura-
tion register for the channel).
I DRNx
D RNx
Open Load
If there is no short to ground or to supply, and the load is not con-
V OCL
I DPU
V DRNx
nected, then the current sources will pull V DRNx towards the open
load clamp voltage, V OCL . V DRNx will then be greater than V STG
but less than V OL and an open load is reported (see figure 3).
GND
Figure 4a. Diagnostic Current Source Circuit
100
The time taken for V DRNx to reach the correct value for an open
fault condition depends on the current sourced from the DRNx
terminal and on the capacitance connected to the drain of the
FET. To avoid false fault detection at switch-off, the outputs
from the short to ground and open load comparators are ignored
80
60
40
20
0
–20
–40
NPD = 0
NPD = 1
I DPD
during the off-state fault blank time, t BL(off) , after the GATx out-
put drives low. One of four possible off-state fault blank times is
selected, per channel, through the TOF0
and TOF1 bits (bits 6 and 7 of the fault configuration register
for the channel).
To avoid false fault detection during supply transients, an addi-
tional fault filter masks faults that are present for less than the
off-state fault filter time, t FF(off) . This fault filter is only active
after the fault blank time.
–60
–80
–100
0
2
4
6
8
10
I DPU
12
The result is that directly after switch-off, a short to ground or
open load fault will not be detected until t BL(off) after the GATx
output is commanded to drive low. If a fault occurs after t BL(off)
from switch-off then it must be present for at least t FF(off) before it
is detected.
Figure 4b. Diagnostic Currents
V DRNx (V)
In some applications, for example when driving high efficiency
LEDs, the load may be sensitive to the pull down current used to
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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