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| 型号： | A3944KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/31页 |
| 文件大小： | 0K |
| 描述： | IC PREDRIVER MOSFET 6CH TSSOP |
| 标准包装： | 8,000 |
| 配置： | 低端 |
| 输入类型： | 并行/串行 |
| 延迟时间： | 200ns |
| 电流 - 峰： | 50mA |
| 配置数： | 6 |
| 输出数： | 6 |
| 电源电压： | 6 V ~ 40 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
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A3944
Address 5: Fault Mask Register
Automotive, Low Side FET Pre-Driver
case the fault registers will continue to alternate between Fault0
The six least significant bits of this register are the fault mask bits
for each of the six channels. K0 corresponds to channel 0, K1 to
channel 1, and so forth. When the K bit for a channel is set to 1
all faults on that channel are ignored and no faults are reported
for that channel. Bit 6 is an open load fault mask bit, OLM, that
disables the open load detection on any channel where NPD is
set to 1.
Addresses 8 to 13: Channel Fault Configuration Registers
These six registers, one per channel, determine the fault threshold
levels, fault blank times, and fault features for each channel. The
MSB is always set to 1. The next three bits, bits 12,13, and 14,
are the channel address bits.
The remaining register addresses are unused. Writing to these
addresses will have no effect on the operation but will still report
the fault register on SO.
Fault Register
In addition to the writable registers there are two fault registers,
Fault0 and Fault1. The register being output is identified by bit
11, which contains a zero for Fault0 and a one for Fault1. Each
time any register is written through the serial interface, one of
the fault registers can be read, MSB first, on the serial output
terminal, SO (see the Serial Interface Timing diagram, figure 2).
Fault0 is output: on the first write after a power-on-reset, after a
RESETN low input, or after a serial fault poll (described in the
next paragraph). Fault1 is then read on the next write. The two
registers then alternate on each successful serial write sequence.
The first, most significant, bit in both fault registers is the fault
register flag, FF (bit 15). This bit is set to one, if any faults have
been detected since the last fault reset. The state of FF appears
on SDO as soon as CSN goes low, allowing the fault status to be
determined without a change in the level of SCK. A serial trans-
fer may be terminated when CSN goes low then high, without
generating a serial read fault, by ensuring that SCK remains high
while CSN is low. This allows the main controller to poll the
A3944 through the serial interface to determine if a fault has been
detected. When this occurs the fault register pointer is reset to the
Fault0 register, so the next full write sequence outputs the Fault0
register. The fault status can also be read, without disturbing any
settings, by writing to one of the unused register addresses. In this
and Fault1.
The next three most significant bits, after FF, in each fault regis-
ter are the system diagnostic bits: UV (bit 14), LR (bit 13), and
OT (bit 12). These provide an indication of undervoltage, logic
reset, and overtemperature faults.
Bit 11 (FR) indicates which of the two fault registers is being
output on SO. This bit is a zero for the Fault0 register and a one
for the Fault1 register.
The least significant 9 bits in each fault register provide three
bits per channel, one bit for each of the three possible fault states:
short to battery, short to ground, and open load. Fault0 con-
tains the fault data for channels 0, 1, and 2. Fault1 contains the
fault data for channels 3, 4, and 5. The bits naming convention
indicates the channel and fault allocation. The format is “ccff,”
where “cc” is C0, C1, C2, C3, C4, or C5 (indicating the channel)
and “ff” is SG, SB, or OL (indicating the faults: short-to-ground,
short-to-battery and open-load respectively).
The contents of the fault register that is being read cannot change
when CSN is low and a serial read is in progress. Any faults
detected during a serial read do affect the read in progress but the
fault will be latched in the fault register when CSN goes high at
the end of a serial read. The fault bits can only be cleared after:
either the diagnostic circuits have confirmed that the fault that
has been reported is no longer present, or there is a low level on
the RESETN input.
In the case of undervoltage or overtemperature faults, which are
not latched, the fault bits will be reset at the end of a serial read if
the fault is not detected at that time.
For channel faults, which are latched, the fault bits will be reset at
the end of a serial read if the diagnostic circuits have previously
determined that the fault that has been reported is no longer pres-
ent. This determination can only occur at the end of a fault blank
time and therefore requires: either an on-to-off transition (for
short to ground and open load faults), or an off-to-on transition
(for short to battery faults) on the faulty channel before the start
of a serial read. Any changes to the fault state when a read is in
progress are ignored until the end of the serial read. If a fault is
cleared when a serial read is in progress, then the fault bits will
be cleared when CSN goes high.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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