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参数资料
| 型号： | A3944KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/31页 |
| 文件大小： | 0K |
| 描述： | IC PREDRIVER MOSFET 6CH TSSOP |
| 标准包装： | 8,000 |
| 配置： | 低端 |
| 输入类型： | 并行/串行 |
| 延迟时间： | 200ns |
| 电流 - 峰： | 50mA |
| 配置数： | 6 |
| 输出数： | 6 |
| 电源电压： | 6 V ~ 40 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
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A3944
Automotive, Low Side FET Pre-Driver
ensure open load detection. In these cases this pull-down current
can be disabled by setting the NPD bit (bit 8 in the fault con-
figuration register for the channel). If the NPD bit is set then it is
possible that V DRNx will reach the correct value for an open fault
condition when the load is connected, resulting in a false open
load detection.
If this is likely, there are two options:
? Set the fault mask bit for the channel. This will mask all faults
on that channel and may not be a suitable option.
? Set the open load fault mask bit, OLM (bit 6 in the fault mask
register). This will disable open load detection on any channel
where NPD is set to 1.
Chip Diagnostics
The chip temperature and the supply voltage levels at VDD and
VREG are monitored to ensure correct and safe operation of the
circuit.
VDD is monitored to ensure that power-up and power-down does
not cause incorrect operation. All outputs will be switched to high
impedance, the VREG regulator will be disabled and all faults
reset when the voltage at VDD, V DD , falls below the undervolt-
age level, V DDUV . The outputs will be reactivated when V DD
rises above the undervoltage turn-on level plus the hysteresis
voltage, defined as V DDUV + V DDUVhys . When V DD rises above
this threshold, all registers will be reset to their power-on state,
and all GATx outputs will be low. In the fault register any latched
channel faults will be reset, the logic reset (LR) and undervoltage
(UV) bits will be set, and the OT bit will reflect the status of the
overtemperature monitor.
VREG is monitored to ensure correct operation of the fault
detection and control circuits. All channel faults will be reset
when the voltage at VREG, V REG , falls below the undervoltage
level, V REGUV . They will be held reset until V REG rises above the
undervoltage lockout level plus the hysteresis voltage, V REGUV
+ V REGUVhys . The outputs will remain active irrespective of the
value of V REG .
The chip temperature is monitored by the thermal warning cir-
cuit. An overtemperature fault will be indicated but no action will
be taken when the chip temperature exceeds the overtemperature
warning level T JW . It is incumbent upon the user to take any nec-
essary action to limit dissipation to reduce the temperature.
Serial Interface
The inputs CSN, SCK, and SI provide a three wire synchronous
serial interface, compatible with SPI, that can be used to control
all features of the A3944. The output, SO, can be used to provide
a fourth interface connection for detailed diagnostic feedback.
The serial interface timing requirements are specified in the Elec-
trical Characteristics table, and illustrated in the Serial Interface
Timing diagram, figure 2. Data is received on the SI terminal and
clocked through a shift register on the rising edge of the clock
signal input on the SCK terminal. CSN is normally held high, and
is only brought low to initiate a serial transfer. No data is clocked
through the shift register when CSN is high, allowing multiple
slave units to use common SI, SCK, and SO connections. Each
slave then requires an independent CSN connection.
When 16 data bits have been clocked into the shift register, CSN
must be taken high to latch the data into the selected register.
When this occurs, the internal control circuits act on the new data
and the fault register is reset.
If there is either: more than 16 rising edges on SCK, or at least
one but fewer than 16 rising edges on SCK and CSN goes high,
then the write will be cancelled without writing data to the regis-
ters or resetting the diagnostic registers. The FF bit will be set to
indicate a data transfer error.
Configuration and Control Registers
The serial data word is 16 bits, input MSB first. The first four bits
are defined as the register address. This provides sixteen write-
able registers:
Address 1: Gate Select Register
The six least significant bits of this register are the control bits
for each of the six channels. G0 corresponds to channel 0, G1 to
channel 1, and so forth. If RESETN is high and no faults are pres-
ent on the channel, then when the Gx bit for a channel is set to 1
the GATx output will be high.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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| A3946KLB-T | 功能描述:IC MOSFET CONTROLLER 16-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器，驱动器 系列:- 标准包装:1 系列:- 应用:直流电机驱动器，步进电机驱动器 评估套件:- 输出数:1 或 2 电流 - 输出:750mA 电压 - 负载:10 V ~ 40 V 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-BFSOP（0.295"，7.50mm 宽） 供应商设备封装:24-SOP 包装:Digi-Reel® 其它名称:MTS62C19A-HS105DKR |
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