参数资料
型号: A3944KLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 23/31页
文件大小: 0K
描述: IC PREDRIVER MOSFET 6CH TSSOP
标准包装: 8,000
配置: 低端
输入类型: 并行/串行
延迟时间: 200ns
电流 - 峰: 50mA
配置数: 6
输出数: 6
电源电压: 6 V ~ 40 V
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 带卷 (TR)
A3944
Automotive, Low Side FET Pre-Driver
the drain clamp in the A3944. The maximum current, the A3944
Note that this equation is only valid for normal load and open
drain clamp maximum current, I DRNC , will be:
P DRNC
I DRNC =
V DCL
where
P DRNC is the A3944 drain clamp maximum power and
V DCL is the A3944 drain clamp voltage.
Substituting into equation 5:
(5)
load conditions when:
V DRNx > V OCL
where V OCL is the open load clamp voltage.
Ideally an open load would mean an infinite or at least a very
large (>1 M Ω ) resistance. In practice this is not necessarily the
case, and the limit of open-load resistance values for correct
detection will be determined by: the threshold voltages, the diag-
nostic currents, and the load voltage.
An open load is detected when:
I DRNC =
100 mW
54 V
= 1.8 mA
V DRNx < V OL
where V OL is the open load detect voltage, then:
As given in equation 1, the value of the drain resistor is the volt-
age across the resistor divided by the maximum current:
? V OL > V DRNx ,
? V OL > V L – I DPD ( R L + R D ) ,
(from 6)
R Dx =
V FET V DCL
I DRNC
∴ R L > [( V L – V OL ) / I DPD ] + R D . (7)
There are two open-load resistance values to consider. The first is
the minimum resistance at which an open load detection is always
R Dx =
60 V – 54 V
1.8 mA
= 3.3 k Ω
guaranteed. The second is the maximum resistance that a load can
present without ever causing an open load to be detected. Both
cases, described below, assume that the load is connected to the
The maximum repetition rate is irrelevant in this case because the
A3944 will sustain the maximum clamp dissipation indefinitely.
load supply and that the load supply is higher than the open load
clamp voltage, V OCL .
V L
Practical Open Load Limits
An open load is detected, when the external FET is off, if the
voltage at the DRNx terminal is less than the open load threshold,
V OL , but greater than the short to ground threshold, V STG . The
voltage at the DRNx terminal in the off-state is defined as (refer-
ring to figure 13):
V DRNx = V L – I DPD ( R L + R D ) (6)
where
+
-
V OL
I DPD
DRNx
R D
R L
V DRNx is the voltage at the DRNx terminal,
V L is the load supply voltage,
I DPD is the diagnostic pull-down current,
R L is the load resistance, and
R D is the DRNx current limit resistor.
V OCL
Figure 13. Open load detection condition
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
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