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参数资料
| 型号： | A4979GLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 16/44页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR MICRO STEP 28TSSOP |
| 特色产品： | A4979 Series |
| 标准包装： | 1 |
| 应用： | 直流电机驱动器，PWM 电机驱动器，步进电机驱动器 |
| 评估套件： | 可供 |
| 输出数： | 1 |
| 电流 - 输出： | 1.5A |
| 电压 - 负载： | 7 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 620-1463-6 |
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A4979
Microstepping Programmable Stepper Motor Driver
With Stall Detect and Short Circuit Protection
Serial Interface Description
A three wire synchronous serial interface, compatible with
SPI, can be used to configure and control all the features of the
A4979. A fourth wire can be used to provide diagnostic feedback.
The registers that are accessible through the serial interface are
defined in table 2.
The A4979 can be operated without using the serial interface,
by using the default configuration and control register settings
and the STEP and DIR logic inputs for motor control. However,
application-specific configurations are only possible by setting
the appropriate register bits through the serial interface. In addi-
tion to setting the configuration bits, the serial interface can also
be used to control the motor directly.
The serial interface timing requirements are specified in the Elec-
trical Characteristics table, and illustrated in figure 1.
Table 2. Serial Register Definition*
Writing to Configuration and Control Registers
When writing to the serial register, data is received on the SDI
pin and clocked through a shift register on the rising edge of the
clock signal input on the SCK pin. STRn is normally held high,
and is only brought low to initiate a serial transfer. No data is
clocked through the shift register when STRn is high, thus allow-
ing multiple SDI slave units to use common SDI, SCK, and SDO
connections. Each independent slave requires a dedicated STRn
connection.
The serial data word has 16 bits, MSB input first. After 16 data
bits have been clocked into the shift register, STRn must be taken
high to latch the data into the selected register. When this occurs,
the internal control circuits act on the new configuration and
control data, and the diagnostic registers are reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Configuration and Control Registers (Write)
Configuration
Register 0
(CONFIG0)
0
0
SYR
1
MS1
0
MS0
0
MXI1
1
MXI0
1
PFD2
1
PFD1
0
PFD0
0
TBK1
0
TBK0
1
TOF2
FRQ2
0
TOF1
FRQ1
0
TOF0
FRQ0
1
PWM
0
Configuration
Register 1
(CONFIG1)
0
1
OSC
0
TSC1
1
TSC0
0
0
0
0
0
0
CD3
1
CD2
0
CD1
0
CD0
0
DIAG1 DIAG0
0 0
Run Register
(RUN)
Table Load
Register
(TBLLD)
1
1
0
1
EN
0
0
OL1
0
0
OL0
1
0
HLR
0
0
SLEW
1
0
BRK
0
0
DCY1
1
0
DCY0
0
PTP
1
SC5
0
PT5
0
SC4
0
PT4
0
SC3
0
PT3
0
SC2
0
PT2
0
SC1
0
PT1
0
SC0
0
PT0
0
Diagnostic Registers (Read)
Fault
Register 0
FF
TW1
TW0
0
UV
ST
OLB
OLA
BML
BMH
BPL
BPH
AML
AMH
APL
APH
(FAULT0)
Fault
Register 1
FF
TW1
TW0
0
UV
ST
OLB
OLA
0
0
SA5
SA4
SA3
SA2
SA1
SA0
(FAULT1)
*Power-on reset value shown below each input register bit.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
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