参数资料
型号: A4979GLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 9/44页
文件大小: 0K
描述: IC MOTOR DRVR MICRO STEP 28TSSOP
特色产品: A4979 Series
标准包装: 1
应用: 直流电机驱动器,PWM 电机驱动器,步进电机驱动器
评估套件: 可供
输出数: 1
电流 - 输出: 1.5A
电压 - 负载: 7 V ~ 50 V
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 标准包装
其它名称: 620-1463-6
A4979
Microstepping Programmable Stepper Motor Driver
With Stall Detect and Short Circuit Protection
Functional Description
The A4979 provides a highly flexible microstepping motor driver
that can be configured via the SPI-compatible serial interface. It
can be controlled with simple Step and Direction inputs, for high
speed stepping applications, or directly through the serial inter-
face by writing a step change value.
The two DMOS full bridges are capable of driving bipolar step-
per motors in full-, half-, quarter-, eighth- and sixteenth-step
modes, at up to 50 V and 1.5 A. The current in each phase of the
stepper motor is regulated by a peak detect PWM current control
scheme that can be programmed to operate in fixed off-time or
fixed frequency. Several decay modes can be selected to reduce
audible motor noise and increase step accuracy. In addition the
phase current tables, which default to a sinusoidal current profile,
can be programmed via the serial interface to create unique
microstep current profiles to further improve motor performance
for specific applications.
The outputs are protected from short circuits, and features for
open load and stalled rotor detection are included. Chip level pro-
tection includes hot and cold thermal warning, overtemperature
shutdown, and undervoltage lockout.
Pin Functions
VBBA, VBBB Main motor supply and chip supply for internal
regulators and charge pump. VBBA and VBBB should be con-
nected together and each decoupled to ground with a low ESR
electrolytic capacitor and a good ceramic capacitor.
Note: Any reference to “VBB” in this specification is defined as
applying to both VBBA and VBBB.
CP1, CP2 Pump capacitor connection for charge pump. Connect
a 100 nF (50 V) ceramic capacitor between CP1 and CP2.
VCP Above-supply voltage for high-side drive. A 100 nF (16 V)
ceramic capacitor should be connected between VCP and VBB to
provide the pump storage reservoir.
VDD Logic supply. Compatible with 3.3 V and 5 V logic. Should
be decoupled to ground with a 100 nF (10 V) ceramic capacitor.
VREG Regulated supply for bridge gate drive. Should be decou-
pled to ground with a 470 nF (10 V) ceramic capacitor.
AGND Analog reference ground. Quiet return for measurement
and input references. Connect to PGND (see Layout section).
PGND Digital and power ground. Connect to supply ground and
AGND (see Layout section).
OAP, OAM Motor connection for phase A. Positive motor phase
current direction is defined as flowing from OAM to OAP.
OBP, OBM Motor connection for phase B. Positive motor phase
current direction is defined as flowing from OBM to OBP.
SENSA Phase A current sense. Connect sense resistor between
SENSA and PGND.
SENSB Phase B current sense. Connect sense resistor between
SENSB and PGND.
REF Reference input to set absolute maximum current level for
both phases. Defaults to internal reference when tied to VDD.
STEP Step logic input. Motor advances on rising edge. Filtered
input with hysteresis.
DIR Direction logic input. Direction changes on the next STEP
rising edge. When high, the Phase Angle Number is increased
on the rising edge of STEP. Has no effect when using the serial
interface. Filtered input with hysteresis.
MS0 Microstep resolution select input.
MS1 Microstep resolution select input.
RESETn Resets faults when pulsed low. Forces low-power shut-
down (sleep) when held low for more than the Reset Shutdown
Width, t RSD . Can be pulled to VBB with 30 k Ω resistor.
ENABLE Controls activity of bridge outputs. When held low,
deactivates the outputs, that is, turns off all output bridge FETs.
Internal logic continues to follow input commands.
SDI Serial data input. 16-bit serial word input MSB first.
SDO Serial data output. High impedance when STRn is high. Out-
puts bit 15 of the diagnostic registers (Fault Register 0 and Fault
Register 1), the Fault Register flag, as soon as STRn goes low.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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