参数资料
| 型号： | ACS8946T |
| 厂商： | Semtech |
| 文件页数： | 20/40页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | LVPECL |
| 输出： | CML，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:4 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 625MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 托盘 |
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 27
www.semtech.com
ACS8946 JAM PLL
Note: (i) With a 50 ohms load on each pin to VDD -2V
Input and Output Interface Terminations
Interfacing to either the same type or electrically different
interface types is illustrated by the following circuit
In applications where the output clocks are always
running, they may be A.C. coupled, allowing the receive
end to be at any common mode voltage, however, the
lines must always be terminated at their characteristic
impedance.
The preferred termination for the CML type output is 50
to VDD, as shown in Figure 14. A.C. coupling may be used
subsequently to translate the levels to other interface
types, e.g. to LVPECL/LVDS as shown in Figure 15.
The example of Figure 17 shows LVPECL to LVPECL
terminations with D.C. coupling, so that the ACS8946
sees an equivalent load of around 50
from the resistor
arrangement at the receiver end. Note that signal levels
given in the accompanying graph are nominal levels at
622.08 MHz, and will change with load.
The preferred termination circuitry for the LVDS signals
between the ACS8525/26/27 and the ACS8946 LVPECL
is shown in Figure 19. The bias for the LVPECL input is set
for A.C. inputs at a mid point of approximately 2 V (with a
3.3 V VDD), as opposed to a normal D.C. coupled bias of
VDD - 2 V. This is due to the push-pull nature of an A.C.
coupled signal.
Note: Where inputs to the ACS8946 are AC coupled,
problems may be experienced with activity detection. This
is due to noise/cross-talk on the inputs being interpreted
as activity. To avoid this, DC couple wherever possible and
if AC coupling must be used, consider offsetting the DC
bias of the N and P signals, see Figure 16.
Table 22 DC Characteristics: CML Output Port
Parameter
Symbol
Minimum
Typical
Maximum
Units
IOUT current source
IOUT
13.3
16
19.2
mA
Single-ended output voltage amplitude with 50
load
to VDD and 50 input impedance into next stage.
VOS
-
400
-
mV
Differential output voltage amplitude with 50
load
to VDD and 50
input impedance into next stage on
both pins.
VOD
-
800
-
mV
Table 23 DC Characteristics: LVPECL Output Port
Parameter
Symbol
Minimum
Typical
Maximum
Units
LVPECL Output Low Voltage (Note (i))
VOL_LVPECL
VDD-2.1
-
VDD-1.62
V
LVPECL Output High Voltage (Note (i))
VOH_LVPECL
VDD-1.45
-
VDD-0.88
V
LVPECL Output Differential Voltage (Note (i))
VOD_LVPECL
0.37
-
1.22
V
Table 24 DC Characteristics: LVTTL/CMOS Output Port
Parameter
Symbol
Minimum
Typical
Maximum
Units
Output Low Voltage @ IOL (MAX)
VOL
--
0.4
V
Output High Voltage @ IOH (MIN)
VOH
2.4
-
V
Low Level Output Current @ VOL = 0.4 V
IOL
2-
-
mA
High Level Output Current @ VOH = 2.4 V
IOH
2-
-
mA
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