参数资料
| 型号： | ACS8946T |
| 厂商： | Semtech |
| 文件页数： | 36/40页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | LVPECL |
| 输出： | CML，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:4 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 625MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页当前第36页第37页第38页第39页第40页
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 5
www.semtech.com
ACS8946 JAM PLL
15
CFG_OUT2
O
LVTTL/
LVCMOS
Configuration pin, used in the configuration on power-up of expected input clock
frequency and Resync selection, by connecting to appropriate pin from the CFG_IN[0:7]
pins as required. See “Configuration” on page 13.
16
ALARMC_CO3
O
LVTTL/
LVCMOS
Activity alarm output for the currently selected input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up, where it is
used as a configuration output pin that may be connected to CFG_IN[0:7] input pins as
required. See “Configuration” on page 13.
17
LOCKB
O
Analog
Lock detect output. This is a pulse-width modulated output current, with each pulse
typically +10
A. The output produces a pulse with a width in proportion to the phase
error seen at the internal phase detector. This pin should be connected via an external
parallel capacitor and resistor to ground. The pin voltage will then give an indication of
phase lock: When low, the device is phase locked; when high the device has frequent
large phase errors and so is not phase locked. The value of the RC components used
determines the time and level of consistency required for lock indication. If LOCKB is
disabled by configuration the LOCKB output is held low.
18
CFG_IN0
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 19
to set the available output rates as shown in Table 11.
19
CFG_IN1
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 18
to set the available output rates as shown in Table 11.
20
CFG_IN2
I
LVTTL/
LVCMOSD
Schmitt
Trigger
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 21
to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1
and OUT2 as in Table 10.
21
CFG_IN3
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 20
to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1
and OUT2 as in Table 10.
22
CFG_IN4
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 23 to
set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins
8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12.
23
CFG_IN5
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 22 to
set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins
8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| ACS8947T | IC JITTER ATT MULT PLL 48-QFN |
| AD10200BZ | IC ADC DUAL 12BIT 68-CLCC |
| AD10242BZ | IC ADC DUAL 12BIT 68-CLCC |
| AD10465BZ | IC ADC DUAL 14BIT 68-CLCC |
| AD13280AZ | IC ADC 12BIT 68CLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ACS8947T | 功能描述:IC JITTER ATT MULT PLL 48-QFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ACS9010 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Optoelectronic |
| ACS9510/50EVB | 制造商:Semtech Corporation 功能描述: |
| ACS9510EVB | 功能描述:EVALUATION BOARD FOR ACS9510 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:ToPSync™ 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
| ACS9510T | 制造商:Semtech Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。