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参数资料
| 型号： | AD5744RCSUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC QUAD 14BIT 1LSB 32TQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD5764(R), AD5744R Product Change 04/Sept/2009 |
| 标准包装： | 500 |
| 设置时间： | 10µs |
| 位数： | 14 |
| 数据接口： | 串行 |
| 转换器数目： | 4 |
| 电压电源： | 模拟和数字，双 ± |
| 功率耗散（最大）： | 387mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电压，双极 |
| 采样率（每秒）： | * |
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Data Sheet
AD5744R
Rev. E | Page 25 of 32
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10). The data bits are positioned in DB15 to DB2, as shown in Table 13.
Table 13. Programming the Data Register
REG2
REG1
REG0
A2
A1
A0
DB15 to DB2
DB1
DB0
0
1
0
DAC address
14-bit DAC data
X
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the
data transfer takes place (see Table 10). The coarse gain register is a 2-bit register that allows the user to select the output range of each
DAC as shown in Table 15.
Table 14. Programming the Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15 to DB2
DB1
DB0
0
1
DAC address
Don’t care
CG1
CG0
Table 15. Output Range Selection
Output Range
CG1
CG0
±10 V (Default)
0
±10.2564 V
0
1
±10.5263 V
1
0
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10). The AD5744R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC
channel by 8 LSBs to +7.75 LSBs in 0.25 LSB steps, as shown in Table 16 and Table 17. The adjustment is made to both the positive full-
scale points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register
coding is twos complement.
Table 16. Programming the Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15 to DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
DAC address
Don’t care
FG5
FG4
FG3
FG2
FG1
FG0
Table 17. Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+7.75 LSBs
0
1
+7.5 LSBs
0
1
0
No Adjustment (Default)
0
7.75 LSBs
1
0
1
8 LSBs
1
0
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