参数资料
型号: AD5744RCSUZ-REEL7
厂商: Analog Devices Inc
文件页数: 30/32页
文件大小: 0K
描述: IC DAC QUAD 14BIT 1LSB 32TQFP
产品培训模块: Data Converter Fundamentals
DAC Architectures
产品变化通告: AD5764(R), AD5744R Product Change 04/Sept/2009
标准包装: 500
设置时间: 10µs
位数: 14
数据接口: 串行
转换器数目: 4
电压电源: 模拟和数字,双 ±
功率耗散(最大): 387mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(7x7)
包装: 带卷 (TR)
输出数目和类型: 4 电压,双极
采样率(每秒): *
Data Sheet
AD5744R
Rev. E | Page 7 of 32
TIMING CHARACTERISTICS
AVDD = 11.4 V to 16.5 V, AVSS = 11.4 V to 16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
13
ns min
24th SCLK falling edge to SYNC rising edge
t6
90
ns min
Minimum SYNC high time
t7
2
ns min
Data setup time
t8
5
ns min
Data hold time
t9
1.7
μs min
SYNC rising edge to LDAC falling edge (all DACs updated)
480
ns min
SYNC rising edge to LDAC falling edge (single DAC updated)
t10
10
ns min
LDAC pulse width low
t11
500
ns max
LDAC falling edge to DAC output response time
t12
10
μs max
DAC output settling time
t13
10
ns min
CLR pulse width low
t14
2
μs max
CLR pulse activation time
25
ns max
SCLK rising edge to SDO valid
t16
13
ns min
SYNC rising edge to SCLK falling edge
t17
2
μs max
SYNC rising edge to DAC output response time (LDAC = 0)
t18
170
ns min
LDAC falling edge to SYNC rising edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
4 Standalone mode only.
5 Measured with the load circuit of Figure 5.
6 Daisy-chain mode only.
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