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参数资料
| 型号： | AD6624A |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | 四通道，100 MSPS的数字接收信号处理器（RSP） |
| 文件页数： | 28/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624A |
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REV. 0
AD6624A
–28–
Table VIII. Channel Address Memory Map (continued)
Ch Address
Register
Bit Width
Comments
A5
A6
A7
A8
BIST Signature for I Path
BIST Signature for Q Path
# of BIST Outputs to Accumulate
RAM BIST Control Register
16
16
20
3
BIST-I
BIST-Q
19
–
0: # of Outputs (Counter Value Read)
2:
D-RAM Fail/Pass
1:
C-RAM Fail/Pass
0:
RAM BIST Enable
9:
Map RCF Data to BIST Registers
8
–
7:
I_SDFS Control
1x:
Separate I and Q SDFS Pulses
01:
SDFS High for Entire Frame
00:
Single SDFS Pulse
6
–
5:
SOWL
1x:
24-Bit Words
01:
16-Bit Words
00:
12-Bit Words
4:
SBMx
3
–
0:
SDIVx[3:0]
A9
Serial Port Control Register
10
Serial Output Frame Timing (Master and Slave)
The SDFS signal transitions accordingly depending on whether
the part is in Master (SBM = 1, Figure 43) or Slave (SBM = 0,
Figure 32) mode. The next rising edge of SCLK after this occurs
will drive the first bit of the serial data on the SDO pin. The
falling edge of SCLK or the subsequent rising edge can then be
used by the DSP to sample the data until the required number
of bits is received (determined by the serial output port word
length). If the DSP has the ability to count bits, the DSP will
know when the complete frame is received. If not, the DSP can
monitor the SDFE pin to determine that the frame is complete.
Serial Port Timing Specifications
Whether the AD6624A serial channel is operated as a Serial
Bus Master or as a Serial Slave, the serial port timing is iden-
tical. Figures 38 to 44 indicate the required timing for each of
the specifications.
SCLK
t
SCLKL
t
SCLK
t
SCLKH
Figure 37. SCLK Timing Requirements
CLK
SCLK
t
DSCLKH
t
SCLKH
t
SCLKL
Figure 38. SCLK Switching Characteristics (Divide by 1)
SCLK
SDI
DATA
t
SSI
t
HSI
Figure 39. Serial Input Data Timing Requirements
SCLK
SDO
I
15
I
14
t
DSDO
I
13
Figure 40. Serial Output Data Switching Characteristics
SCLK
SDFS
t
SSF
t
HSF
Figure 41. SDFS Timing Requirements (SBM = 0)
SDO
I
MSB
SDFS
SCLK
t
DSO
I
MSB1
SDFS MINIMUM
WIDTH IS ONE SCLK
FIRST DATA IS AVAILABLE THE FIRST
RISING SCLK AFTER SDFS GOES HIGH
Figure 42. Timing for Serial Output Port (SBM = 1)
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