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参数资料
| 型号： | AD6624A |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | 四通道，100 MSPS的数字接收信号处理器（RSP） |
| 文件页数： | 8/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624A |
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REV. 0
AD6624A
–8–
TIMING DIAGRAMS—INM MICROPORT MODE
CLK
RD
(
DS
)
WR
(RW)
CS
A[2:0]
D[7:0]
RDY
(
DTACK
)
t
SC
t
HC
t
HWR
t
SAM
t
SAM
t
HAM
t
DRDY
VALID DATA
VALID ADDRESS
t
HAM
t
ACC
NOTES
1. t
ACC
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS
MEASURED FROM FE OF
WR
TO THE RE OF RDY.
2. t
ACC
REQUIRES A MAXIMUM 9 CLK PERIODS.
Figure 14. INM Microport Write Timing Requirements
CLK
RD
(
DS
)
WR
(RW)
A[2:0]
D[7:0]
RDY
(
DTACK
)
t
SC
t
SAM
t
ZD
t
DRDY
VALID DATA
VALID ADDRESS
t
ACC
t
HC
CS
t
ZD
t
HAM
NOTES
1.
t
ACC
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS
TIME IS MEASURED FROM FE OF
WR
TO THE RE OF RDY.
2.
t
ACC
REQUIRES A MAXIMUM OF 13 CLK PERIODS AND APPLIES TO
A[2:0] = 7, 6, 5, 3, 2, 1
t
DD
Figure 15. INM Microport Read Timing Requirements
TIMING DIAGRAMS—MNM MICROPORT MODE
CLK
DS
(
RD
)
CS
A[2:0]
D[7:0]
DTACK
(RDY)
t
SC
t
HC
t
HRW
t
SAM
t
SAM
t
HAM
VALID DATA
VALID ADDRESS
t
HAM
t
ACC
NOTES
1.
t
ACC
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS
MEASURED FROM FE OF
DS
TO THE FE OF
DTACK
.
2.
t
ACC
REQUIRES A MAXIMUM 9 CLK PERIODS.
RW(
WR
)
t
DDTACK
t
HDS
Figure 16. MNM Microport Write Timing Requirements
CLK
RD
(
DS
)
WR
(RW)
A[2:0]
D[7:0]
DTACK
(
RDY)
t
SC
t
SAM
t
ZD
VALID DATA
VALID ADDRESS
t
ACC
t
HC
CS
t
ZD
t
HAM
t
DD
t
DDTACK
t
HDS
NOTES
1.
t
ACC
ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS
MEASURED FROM FE OF
DS
TO THE FE OF
DTACK
.
2.
t
ACC
REQUIRES A MAXIMUM 13 CLK PERIODS.
Figure 17. MNM Microport Read Timing Requirements
相关PDF资料 |
PDF描述 |
|---|---|
| AD6624AABC | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6630AR-REEL | Differential, Low Noise IF Gain Block with Output Clamping |
| AD6630AR | Differential, Low Noise IF Gain Block with Output Clamping |
| AD6630PCB | Differential, Low Noise IF Gain Block with Output Clamping |
| AD6630R | Differential, Low Noise IF Gain Block with Output Clamping |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6624AABC | 制造商:Advanced Micro Devices 功能描述: |
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| AD6624AS | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
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