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参数资料
| 型号： | AD6624A |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | 四通道，100 MSPS的数字接收信号处理器（RSP） |
| 文件页数： | 33/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624A |
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REV. 0
AD6624A
–33–
External Memory Map
The External Memory Map is used to gain access to the Channel
Address Space described previously. The 8-bit data and address
registers referenced by the external interface registers can be seen
in the Table XI. (These registers are collectively referred to as
the External Interface Registers since they control all accesses to
the Channel Address space as well as global chip functions.) The
use of each of these individual registers is described below in detail.
It should be noted that the Serial Control interface to Channel 0
has the same memory map as the microport interface and can carry
out
exactly
the same functions, although at a slower rate.
Table XI. External Memory Map
A[2:0] Name
Comment
111
Access Control Register (ACR)
7:
6:
5
–
2:
1
–
0:
7
–
0:
Auto Increment
Broadcast
Instruction[3:0]
A[9:8]
A[7:0]
110
101
Channel Address Register (CAR)
SOFT_SYNC Control Register
(Write Only)
7:
6:
5:
4:
3:
2:
1:
0:
PN_EN
Test_MUX_Select
Hop
Start
SYNC 3
SYNC 2
SYNC 1
SYNC 0
100
PIN_SYNC Control Register
(Write Only)
7:
Toggle IEN for
BIST
First SYNC Only
Hop_En
Start_En
SYNC_EN 3
SYNC_EN 2
SYNC_EN 1
SYNC_EN 0
6:
5:
4:
3:
2:
1:
0:
011
SLEEP
(Write Only)
7
–
6:
5:
Reserved
Access Input Port
Control Registers
Serial Read 0
SLEEP
SLEEP 2
SLEEP 1
SLEEP 0
Reserved
D [19:16]
15
–
8: D [15:8]
7
–
0:
D [7:0]
External
4:
3:
2:
1:
0:
7
–
4:
3
–
0:
010
Data Register 2 (DR2)
001
000
Data Register 1 (DR1)
Data Register 0 (DR0)
0xA9: Serial Port Control Register
This register controls the serial port of the AD6624A and, along with
the RCF control register, it helps to determine the output format.
Bit 9
of this register allows the RCF or CIC5 data to be mapped to
the BIST registers at addresses 0xA5 and 0xA6. When this bit is 0,
the BIST register is in signature mode and ready for a self-test to
be run. When this bit is 1, the output data from the RCF after
formatting or the CIC5 data is mapped to these registers and can
be read through the microport. In addition, when this bit is high,
the DR pin for the channel delivers a 1 CLK cycle wide pulse that
can be used to synchronize the host processor with the AD6624A.
This signal is a 1 SCLK cycle wide pulse when this bit is 0.
Bits 8 and 7
control the output format of the SDFS pulse. When
these bits are 00, there is a single SCLK cycle wide pulse for the I
and Q data. When these bits are 01, the SDFS signal is high for all
of the bits shifted during the serial frame. When these bits are 10 or
11, there are two SDFS pulses that are each 1 SCLK cycle wide.
One pulse precedes the I word of data and the second precedes the
Q word of data. When a serial port is configured as a serial slave, it
should be in the first mode with these bits set to 00.
Bits 6 and 5
determine the serial word length used by the serial
port. If these bits are 00, the serial ports use 12-bit words and shift
12 bits of I followed by 12 bits of Q with each shifted MSB first. If
these bits are 01, the serial ports use 16-bit words and shift 16 bits
of I followed by 16 bits of Q with each shifted MSB first. If these
bits are 1x, the serial ports use 24-bit words and shift 24 bits of I
followed by 24 bits of Q with each shifted MSB first. When the
fixed point output option is chosen from the RCF control register,
these bits also set the rounding correctly in the output formatter of
the RCF.
Bit 4
of this register controls whether the Serial Port is a master or
slave. This register powers up low so that the serial port is a slave in
order to avoid contention problems on the output drivers. The
serial port for channel 0 does not use this bit. The master/slave
status of Serial Port 0 is set by the SBM0 pin.
Bits 3
–
0
control the rate of the SCLK signal when the channel is
master. This four-bit bus can set the SCLK as a division of the
master CLK from 1 to 16 with approximately a 50% duty
cycle. The SCLK can be generated and run up to a maximum
of 80 MHz. The serial division bits from this register are not
used for serial port 0. The external SDIV [3:0] pins are used
to determine this for Serial Port 0.
MICROPORT CONTROL
The AD6624A has an 8-bit microprocessor port and four serial
input ports. The use of each of these ports is described separately
below. The interaction of the ports is then described. The
microport interface is a multimode interface that is designed to
give flexibility when dealing with the host processor. There are two
modes of bus operation: Intel nonmultiplexed mode (INM), and
Motorola nonmultiplexed mode (MNM). The mode is selected
based on host processor and which mode is best suited to that
processor. The microport has an 8-bit data bus (D[7:0]), 3-bit
address bus (A[2:0]), three control pins lines (
CS
,
DS
or
RD
, RW
or
WR
), and one status pin (
DTACK
or RDY). The functionality
of the control signals and status line changes slightly, depending
upon the mode that is chosen. Refer to the timing diagrams and
the following descriptions for details on the operation of both modes.
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