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参数资料
| 型号： | AD6624A |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | 四通道，100 MSPS的数字接收信号处理器（RSP） |
| 文件页数： | 29/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624A |
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REV. 0
AD6624A
–29–
SCLK
SDFS
SDFE
t
DSDFS
t
DSDFE
Figure 43. Serial Frame Switching Characteristics (SBM = 1)
SCLK
SDO
SDFE
t
DSDO
t
DSDFE
Q
1
Q
0
I
14
I
15
Figure 44. SDO, SDFE Switching Characteristics
SBM0
SBM0 is the Serial Bus Master pin for the Channel 0 Serial Port
only. Serial Ports 1, 2, and 3 will always default to Serial Slave
mode but can be programmed as masters in the internal register
space. The SBM0 pin gives the user the option to boot the
AD6624A through Serial Port 0 as a master. When SBM0 is high
(master mode), the AD6624A generates SCLK0 and SDFS0.
When SBM0 is low (slave mode), the AD6624A accepts external
SCLK0 and SDFS0 signals. When configured as a bus master,
the SCLK0 signal can be used to strobe data into the DSP
interface. When used with another AD6624A in Serial Cascade
mode, SCLK0 can be taken from the master AD6624A and
used to shift data out from the cascaded device. In this situation,
SDFS of the slave AD6624A channel is connected to the SDFE
pin of the master AD6624A channel (or the preceding chip in
the chain). When an AD6624A is in Serial Slave mode, all of the
serial port activities are controlled by the external signals SCLK
and SDFS.
Regardless of whether the chip is a Serial Bus Master or is in
Serial Slave mode, the AD6624A Serial Port functions are identical
except for the source of the SCLK and SDFS pins.
SCLK
SCLK is an output when SBM (SBM0 or register bit for Serial
Ports 1, 2, and 3) is high; SCLK is an input when SBM (SBM0
or register bit for Serial Ports 1, 2, and 3) is low in serial slave
mode. In either case, the SDIN input is sampled on the falling
edge of SCLK and all outputs are switched on the rising edge of
SCLK. The SDFS pin is sampled on the falling edge of SCLK.
This allows the AD6624A to recognize the SDFS in time to
initiate a frame on the very next SCLK rising edge. The maximum
speed of this port is 80 MHz.
SDIN
SDIN is the Serial Data Input. Serial Data is sampled on the
falling edge of SCLK. This pin is used in the serial control mode
to write the internal control registers of the AD6624A. These
activities are described later in the Serial Port Control section. The
Serial Input Port is self-framing and bears no fixed relationship to
either SDFS or SDFE.
SDO
SDO is the Serial Data Output. Serial output data is shifted on
the rising edge of SCLK. On the very next SCLK rising edge
after an SDFS, the MSB of the I data from the channel is shifted.
On every subsequent SCLK edge, a new piece of data is shifted
out on the SDO pin until the last bit of data is shifted out. The
last bit of data shifted is the LSB of the Channel
’
s Q data. SDO
is three-stated when the serial port is outside its time-slot. This
allows the AD6624A to share the SDIN of a DSP with other
AD6624s or other devices.
SDFS
SDFS is the Serial Data Frame Sync signal. SDFS is an output
when SBM (SBM0 or register bit for Serial Ports 1, 2, and 3)
is high in the Master mode. SDFS is an input when SBM
(SBM0 or register bit for Serial Ports 1, 2, and 3) is low in the
Slave mode. SDFS is sampled on the falling edge of SCLK.
When SBM is sampled low, the AD6624A serial port will function
as a serial slave. In this mode, the port is silent until the DSP
issues a frame sync. When the AD6624A detects an SDFS on
the falling edge of a DSP-generated serial clock, on the next
rising edge of the serial clock, the AD6624A enables the output
driver and shifts the MSB of the I word. Data is shifted until the
LSB of the Q word has been sent. On the LSB of the Q word,
the AD6624A generates an SDFE, which can be cascaded to the
next SDFS on a TDM serial chain or to the DSP to indicate that
the last bit has been sent.
When SBM is sampled high, the chip functions as a serial bus
master. In this mode, the AD6624A is responsible for generating
serial control data. Three modes of that operation are set via
channel address 0xA9 Bits 8
–
7. Each behaves a little differently,
as detailed below.
In the first mode (0xA9 Bits 8
–
7:00), the SDFS is valid for one
complete clock cycle prior to the data shift. On the next clock cycle,
the AD6624A begins shifting serial data. In the second mode,
(0xA9 Bits 8
–
7:01), the SDFS is high for the entire time that
valid bits are being shifted. The SDFS bit goes high concurrent
with the first bit shifted out of the AD6624A and returns low
after the last bit is shifted out of the AD6624A. In the third
mode (0xA9 Bits 8
–
7:10), the SDFS bit goes high as in the first
mode, one clock cycle prior to the actual data. However, a second
SDFS is inserted one clock cycle prior to the shift of the first Q bit.
In this manner, each word out of the AD6624A is accompanied by
an SDFS.
SDFE
SDFE is the Serial Data Frame End output. SDFE will go high
during the last SCLK cycle (LSB of the Q word) of an active
time-slot. The SDFE output of a master AD6624A channel can
be tied to the input SDFS of an AD6624A channel in Serial
Slave mode in order to provide a hard-wired time-slot scenario.
When the last bit of SDO data is shifted out of the Master
AD6624A, the SDFE signal will be driven high by the same
SCLK rising edge on which this bit is clocked out. On the
falling edge of this SCLK cycle, the slaved serial port will sample
its SDFS signal, which is hard-wired to the SDFE of the master.
On the very next SCLK rising edge, data of the slave will start
shifting. There will be no rest between the time slots of the master
and slave.
Serial Word Length
Bits 6
–
5 of register 0xA9 determine the length of the serial word
(I or Q). If these bits are set to
‘
00,
’
each word is 12 bits (12 bits
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