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| 型号： | AD7190BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH 24BIT W/PGA 24TSSOP |
| 设计资源： | Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，双极；4 个伪差分，双极 |
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Data Sheet
AD7190
Rev. C | Page 19 of 40
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip
registers, which are described in the following sections. In the
descriptions, set implies a Logic 1 state and cleared implies a
Logic 0 state, unless otherwise noted.
COMMUNICATIONS REGISTER
(RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All
communications to the part must start with a write operation to
the communications register. The data written to the communi-
cations register determines whether the next operation is a read
or write operation and in which register this operation takes
place. For read or write operations, when the subsequent read
or write operation to the selected register is complete, the
interface returns to where it expects a write operation to
the communications register. This is the default state of the
interface and, on power-up or after a reset, the ADC is in this
default state waiting for a write operation to the communi-
cations register. In situations where the interface sequence is
lost, a write operation of at least 40 serial clock cycles with DIN
high returns the ADC to this default state by resetting the entire
part. Table 14 outlines the bit designations for the
communications register. CR0 through CR7 indicate the bit
locations, CR denoting that the bits are in the communications
register. CR7 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default
status of that bit.
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
WEN(0)
R/W(0)
RS2(0)
RS1(0)
RS0(0)
CREAD(0)
0(0)
Table 14. Communications Register Bit Designations
Bit Location
Bit Name
Description
CR7
WEN
Write enable bit. A 0 must be written to this bit for a write to the communications register to occur. If a 1 is
the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location
until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the
communications register.
CR6
R/W
A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position
indicates that the next operation is a read from the designated register.
CR5 to CR3
RS2 to RS0
Register address bits. These address bits are used to select which registers of the ADC are selected during
the serial interface communication. See Table 15.
CR2
CREAD
Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured so that the data register can be continuously read; that is, the contents of the data
register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin
goes low to indicate that a conversion is complete. The communications register does not have to be
written to for subsequent data reads. To enable continuous read, the instruction 01011100 must be written
to the communications register. To disable continuous read, the instruction 01011000 must be written to
the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors
activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset
occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be
written to the device.
CR1 to CR0
These bits must be programmed to Logic 0 for correct operation.
Table 15. Register Selection
RS2
RS1
RS0
Register
Register Size
0
Communications register during a write operation
8 bits
0
Status register during a read operation
8 bits
0
1
Mode register
24 bits
0
1
0
Configuration register
24 bits
0
1
Data register/data register plus status information
24 bits/32 bits
1
0
ID register
8 bits
1
0
1
GPOCON register
8 bits
1
0
Offset register
24 bits
1
Full-scale register
24 bits
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