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| 型号： | AD7190BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH 24BIT W/PGA 24TSSOP |
| 设计资源： | Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，双极；4 个伪差分，双极 |
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AD7190
Data Sheet
Rev. C | Page 26 of 40
ADC CIRCUIT INFORMATION
MCLK1 MCLK2
P0/REFIN2(–) P1/REFIN2(+)
DVDD DGND
5V
AIN1
IN+
IN–
OUT–
OUT+
AIN2
AIN3
AIN4
AINCOM
REFIN1(–)
BPDSW
AGND
AD7190
REFIN1(+)
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
TEMP
SENSOR
CLOCK
CIRCUITRY
AVDD
AGND
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
AVDD
AGND
Σ-Δ
ADC
PGA
MUX
07640-
012
Figure 18. Basic Connection Diagram
OVERVIEW
The AD7190 is an ultralow noise ADC that incorporates a
∑- modulator, a buffer, PGA, and on-chip digital filtering
intended for the measurement of wide dynamic range signals
such as those in pressure transducers, weigh scales, and strain
gauge applications.
The part can be configured to have two differential inputs or four
pseudo differential inputs that can be buffered or unbuffered.
Figure 18 shows the basic connections required to operate the part.
FILTER, OUTPUT DATA RATE, SETTLING TIME
A ∑- ADC consists of a modulator followed by a digital filter.
The AD7190 has two filter options: a sinc3 filter and a sinc4
filter. The filter is selected using the SINC3 bit in the mode
register. When SINC3 is set to 0 (default value), the sinc4 filter is
selected. The sinc3 filter is selected when SINC3 is set to 1.
At low output data rates (<1 kHz), the noise-free resolution is
comparable for the two filter types. However, at the higher
output data rates, the sinc4 filter gives better noise free
resolution.
The sinc4 filter also leads to better 50 Hz and 60 Hz rejection.
While the notch positions are not affected by the order of the
filter, the higher order filter has wider notches, which leads to
better rejection in the band (±1 Hz) around the notches. It also
gives better stop-band attenuation. The benefit of the sinc3 filter
is its lower settling time for the same output data rate.
Chop Disabled
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
fADC = fCLK/(1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK = master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to 4800 Hz;
that is, FS[9:0] can have a value from 1 to 1023.
The previous equation is valid for both the sinc3 and sinc4
filters. The settling time for the sinc4 filter is equal to
tSETTLE = 4/fADC
Whereas the settling time for the sinc3 filter is equal to
tSETTLE = 3/fADC
Figure 19 and Figure 20 show the frequency response of the sinc4
and sinc3 filters, respectively, for an output data rate of 50 Hz.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
013
Figure 19. Sinc4 Filter Response (50 Hz Output Data Rate)
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| AD7190WBRUZ | 功能描述:24 Bit Analog to Digital Converter 2, 4 Input 1 Sigma-Delta 24-TSSOP 制造商:analog devices inc. 系列:- 包装:管件 零件状态:有效 位数:24 采样率（每秒）:4.8k 输入数:2，4 输入类型:差分，个伪差分 数据接口:SPI，DSP 配置:MUX-PGA-ADC 无线电 - S/H:ADC:- A/D 转换器数:1 架构:三角积分 参考类型:外部， 内部 电压 - 电源，模拟:5V 电压 - 电源，数字:2.7 V ~ 5.25 V 特性:PGA，温度传感器 工作温度:-40°C ~ 105°C 封装/外壳:24-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:24-TSSOP 标准包装:1 |
| AD7190WBRUZ-RL | 制造商:Analog Devices 功能描述: |
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| AD7191A/0B | 制造商:Sony Nec Optiarc America 功能描述:DOUBLE DUAL INTERNAL DVDRW PATA BEZEL 20X/18X12XRAM - Bulk |
| AD7191BRUZ | 功能描述:IC ADC 2CH 24B SD 24TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
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