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| 型号： | AD7190BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH 24BIT W/PGA 24TSSOP |
| 设计资源： | Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，双极；4 个伪差分，双极 |
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AD7190
Data Sheet
Rev. C | Page 22 of 40
Table 18. Operating Modes
MD2
MD1
MD0
Mode
0
Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions
and places the result in the data register. The DOUT/ RDY pin and the RDY bit in the status register go low when a
conversion is complete. The user can read these conversions by setting the CREAD bit in the communications
register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each
conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the
complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are
available at the selected output data rate, which is dependent on filter choice.
0
1
Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single
conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then
performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in
the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data
register and RDY remains active (low) until the data is read or another conversion is performed.
0
1
0
Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are
still provided.
0
1
Power-down mode. In power-down mode, all AD7190 circuitry, except the bridge power-down switch, is powered
down. The bridge power-down switch remains active because the user may need to power up the sensor prior to
powering up the AD7190 for settling reasons. The external crystal, if selected, remains active.
1
0
Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the
calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measured offset coefficient is placed in the offset register of the selected channel.
1
0
1
Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed
in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the
selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-
scale error.
1
0
System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required
each time the gain of a channel is changed.
1
System full-scale calibration. The user should connect the system full-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required
each time the gain of a channel is changed.
CONFIGURATION REGISTER
(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)
The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to
configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the
gain, and to select the analog input channel.
Table 19 outlines the bit designations for the configuration register. CON0 through CON23 indicate the bit locations. CON denotes that
the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-
on/reset default status of that bit.
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| AD7190WBRUZ | 功能描述:24 Bit Analog to Digital Converter 2, 4 Input 1 Sigma-Delta 24-TSSOP 制造商:analog devices inc. 系列:- 包装:管件 零件状态:有效 位数:24 采样率（每秒）:4.8k 输入数:2，4 输入类型:差分，个伪差分 数据接口:SPI，DSP 配置:MUX-PGA-ADC 无线电 - S/H:ADC:- A/D 转换器数:1 架构:三角积分 参考类型:外部， 内部 电压 - 电源，模拟:5V 电压 - 电源，数字:2.7 V ~ 5.25 V 特性:PGA，温度传感器 工作温度:-40°C ~ 105°C 封装/外壳:24-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:24-TSSOP 标准包装:1 |
| AD7190WBRUZ-RL | 制造商:Analog Devices 功能描述: |
| AD7191 | 制造商:AD 制造商全称:Analog Devices 功能描述:Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors |
| AD7191A/0B | 制造商:Sony Nec Optiarc America 功能描述:DOUBLE DUAL INTERNAL DVDRW PATA BEZEL 20X/18X12XRAM - Bulk |
| AD7191BRUZ | 功能描述:IC ADC 2CH 24B SD 24TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
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