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参数资料
| 型号： | AD73322LARUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/43页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR FRONTEND DL 28TSSOP |
| 标准包装： | 2,500 |
| 位数： | 16 |
| 通道数： | 4 |
| 功率（瓦特）： | 73mW |
| 电压 - 电源，模拟： | 2.7 V ~ 5.5 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.5 V |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
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AD73322
–25–
REV. B
In a single AD73322 configuration, each 16-bit data frame sent
from the DSP to the device is interpreted as DAC data, but it is
necessary to send two DAC words per sample period in order to
ensure DAC update. Also, as the device count setting defaults
to 1, it must be set to 2 (001b) to ensure correct update of both
DACs on the AD73322.
Appendix B details the initialization and operation of an AD73322
in normal Data Mode.
SE
SDOFS
SCLK
SDO
SDIFS
SDI
ADC SAMPLE WORD (DEVICE 2)
ADC SAMPLE WORD (DEVICE 1)
DAC DATA WORD (DEVICE 2)
DAC DATA WORD (DEVICE 1)
Figure 16. Interface Signal Timing for Data Mode
Operation
Mixed Program/Data Mode
This mode allows the user to send control words to the device
along with the DAC data. This permits adaptive control of the
device whereby control of the input/output gains etc., can be
affected by interleaving control words along with the normal
flow of DAC data. The standard data frame remains 16 bits, but
now the MSB is used as a flag bit to indicate whether the re-
maining 15 bits of the frame represent DAC data or control
information. In the case of DAC data, the 15 bits are loaded
with MSB justification and LSB set to 0 to the DAC register.
Mixed mode is enabled by setting the MM bit (CRA:1) to 1 and
the DATA/PGM bit (CRA:0) to 1. In the case where control
setting changes will be required during normal operation, this
mode allows the ability to load both control and data informa-
tion with the slight inconvenience of formatting the data. Note
that the output samples from the ADC will also have the MSB
set to zero to indicate it is a data word.
Appendix C details the initialization and operation of an AD73322
operating in mixed mode. Note that it is not essential to load
the control registers in Program Mode before setting mixed
mode active. It is also possible to initiate mixed mode by pro-
gramming CRA with the first control word and then interleaving
control words with DAC data.
Digital Loop-Back
This mode can be used for diagnostic purposes and allows the
user to feed the ADC samples from the ADC register directly to
the DAC register. This forms a loop-back of the analog input to
the analog output by reconstructing the encoded signal using
the decoder channel. The serial interface will continue to work,
which allows the user to control gain settings, etc. Only when
DLB is enabled with mixed mode operation can the user disable
the DLB, otherwise the device must be reset.
SPORT Loop-Back
This mode allows the user to verify the DSP interfacing and
connection by writing words to the SPORT of the devices and
have them returned back unchanged after a delay of 16 SCLK
cycles. The frame sync and data word that are sent to the device
are returned via the output port. Again, SLB mode can only be
disabled when used in conjunction with mixed mode, otherwise
the device must be reset.
Analog Loop-Back
In Analog Loop-Back mode, the differential DAC output is
connected, via a loop-back switch, to the ADC input (see Figure
17). This mode allows the ADC channel to check functionality
of the DAC channel as the reconstructed output signal can be
monitored using the ADC as a sampler. Analog Loop-Back is
enabled by setting the ALB bit (CRF:7).
NOTE: Analog Loop-Back can only be enabled if the Analog
Gain Tap is powered down (CRC:1 = 0).
INVERTING
OP AMPS
ANALOG
LOOP-BACK
SELECT
INVERT
SINGLE-
ENDED
ENABLE
GAIN
1
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
VREF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
REFERENCE
0/38dB
PGA
AD73322
VREF
ANALOG GAIN
TAP POWERED
DOWN
Figure 17. Analog Loop-Back Connectivity
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LARZ | 功能描述:IC ANALOG FRONT END DUAL 28-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARZ-REEL | 制造商:Analog Devices 功能描述:DUAL-CHANNEL, 3 V FRONT-END PROCESSOR FOR GENERAL PURPOSE - Tape and Reel |
| AD73322LAST | 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD73322LAST-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 44-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LASTZ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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