参数资料
型号: AD73322LARUZ-REEL
厂商: Analog Devices Inc
文件页数: 6/43页
文件大小: 0K
描述: IC PROCESSOR FRONTEND DL 28TSSOP
标准包装: 2,500
位数: 16
通道数: 4
功率(瓦特): 73mW
电压 - 电源,模拟: 2.7 V ~ 5.5 V
电压 - 电源,数字: 2.7 V ~ 5.5 V
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
AD73322
–14–
REV. B
GAIN
1
INVERT
SINGLE-ENDED
ENABLE
0/38dB
PGA
DECIMATOR
SERIAL
I/O
PORT
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
SWITCHED
CAPACITOR
LOW-PASS
FILTER
DIGITAL
SIGMA-
DELTA
MODULATOR
GAIN
1
INTER-
POLATOR
VREF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
DECIMATOR
+6/–15dB
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
SWITCHED
CAPACITOR
LOW-PASS
FILTER
DIGITAL
SIGMA-
DELTA
MODULATOR
GAIN
1
INTER-
POLATOR
VREF
VFBN2
VINN2
VINP2
VFBP2
VOUTP2
VOUTN2
AD73322
AGND1
AGND2
DGND
SDOFS
SDO
MCLK
SE
RESET
SCLK
SDIFS
SDI
DVDD
AVDD2
AVDD1
REFERENCE
PGA
ANALOG
SIGMA-DELTA
MODULATOR
ANALOG
LOOP
BACK
GAIN
1
INVERT
SINGLE-ENDED
ENABLE
0/38dB
PGA
ANALOG
SIGMA-DELTA
MODULATOR
ANALOG
LOOP
BACK
Figure 9. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filter-
ing. Due to the high level of oversampling, the input antialias
requirements are reduced such that a simple single pole RC
stage is sufficient to give adequate attenuation in the band of
interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
Table IV. PGA Settings for the Encoder Channel
IGS2
IGS1
IGS0
Gain (dB)
00
0
00
1
6
01
0
12
01
1
18
10
0
20
10
1
26
11
0
32
11
1
38
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