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| 型号： | AD73322LARUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/43页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR FRONTEND DL 28TSSOP |
| 标准包装： | 2,500 |
| 位数： | 16 |
| 通道数： | 4 |
| 功率（瓦特）： | 73mW |
| 电压 - 电源，模拟： | 2.7 V ~ 5.5 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.5 V |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
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AD73322
–33–
REV. B
Digital Interfacing
The AD73322 is designed to easily interface to most common
DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be
connected to the DSP’s Serial Clock, Receive Data, Receive
Data Frame Sync, Transmit Data and Transmit Data Frame
Sync pins respectively. The SE pin may be controlled from a
parallel output pin or flag pin such as FL0-2 on the ADSP-21xx
(or XF on the TMS320C5x) or, where SPORT powerdown is
not required, it can be permanently strapped high using a suit-
able pull-up resistor. The RESET pin may be connected to the
system hardware reset structure or it may also be controlled
using a dedicated control line. In the event of tying it to the
global system reset, it is advisable to operate the device in mixed
mode, which allows a software reset, otherwise there is no
convenient way of resetting the device. Figures 38 and 39
show typical connections to an ADSP-218x and TMS320C5x
respectively.
TFS
DT
SCLK
DR
RFS
ADSP-218x
DSP
AD73322
CODEC
SDIFS
SDI
SCLK
SDO
SDOFS
FL0
FL1
RESET
SE
Figure 38. AD73322 Connected to ADSP-218x
FSX
DT
CLKX
DR
FSR
TMS320C5x
DSP
AD73322
CODEC
SDIFS
SDI
SCLK
SDO
SDOFS
XF
RESET
SE
CLKR
Figure 39. AD73322 Connected to TMS320C5x
Cascade Operation
Where it is required to configure a cascade of up to eight codecs
(4 AD73322 dual codecs), it is necessary to ensure that the
timing of the SE and RESET signals is synchronized at each
device in the cascade. A simple D type flip flop is sufficient to
sync each signal to the master clock MCLK, as in Figure 40.
1/2
74HC74
CLK
DQ
DSP CONTROL
TO SE
MCLK
SE SIGNAL SYNCHRONIZED
TO MCLK
1/2
74HC74
CLK
DQ
DSP CONTROL
TO
RESET
MCLK
RESET SIGNAL SYNCHRONIZED
TO MCLK
Figure 40. SE and RESET Sync Circuit for Cascaded
Operation
Connection of a cascade of devices to a DSP, as shown in Fig-
ure 41, is no more complicated than connecting a single device.
Instead of connecting the SDO and SDOFS to the DSP’s Rx
port, these are now daisy-chained to the SDI and SDIFS of the
next device in the cascade. The SDO and SDOFS of the final
device in the cascade are connected to the DSP’s Rx port to
complete the cascade. SE and RESET on all devices are fed
from the signals that were synchronized with the MCLK using
the circuit as described above. The SCLK from only one device
need be connected to the DSP’s SCLK input(s) as all devices
will be running at the same SCLK frequency and phase.
TFS
DT
DR
RFS
AD73322
CODEC
SDIFS
SDI
SCLK
SDO
SDOFS
SCLK
DEVICE 1
MCLK
SE
RESET
AD73322
CODEC
SDIFS
SDI
SCLK
SDO
SDOFS
DEVICE 2
MCLK
SE
RESET
74HC74
Q1
Q2
D1
D2
FL0
FL1
ADSP-218x
DSP
Figure 41. Connection of Two AD73322s Cascaded to
ADSP-218x
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PDF描述 |
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| AD73322LYRZ | IC ANALOG FRONT END DUAL 28-SOIC |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LARZ | 功能描述:IC ANALOG FRONT END DUAL 28-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARZ-REEL | 制造商:Analog Devices 功能描述:DUAL-CHANNEL, 3 V FRONT-END PROCESSOR FOR GENERAL PURPOSE - Tape and Reel |
| AD73322LAST | 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD73322LAST-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 44-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LASTZ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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