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参数资料
| 型号： | AD73460 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | 六输入通道模拟前端 |
| 文件页数： | 21/32页 |
| 文件大小： | 290K |
| 代理商： | AD73460 |
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AD73460
–21–
REV. 0
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the AD73460 to fetch two operands in a single cycle, one
from program memory and one from data memory. The AD73460
can fetch an operand from program memory and the next
instruction in the same cycle.
In lieu of the address and data bus for external memory connec-
tion, the AD73460 may be configured for 16-bit Internal DMA
port (IDMA port) connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH, and
BG). One execution mode (Go Mode) allows the AD73460 to
continue running from on-chip memory. Normal execution
mode requires the processor to halt while buses are granted.
The AD73460 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET
signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The AD73460 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every
n
pro-
cessor cycle, where
n
is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The AD73460 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the AD73460 SPORTs.
For additional information on Serial Ports, refer to the
ADSP-
2100 Family User
’
s Manual
, Third Edition.
SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
SPORTs can use an external serial clock or generate their
own serial clock internally.
SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and
μ
-law companding according
to CCITT recommendation G.711.
SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
DSP SECTION PIN DESCRIPTIONS
The AD73460 is available in a 119-ball PBGA package. In order
to maintain maximum functionality and reduce package size and
pin count, some serial port, programmable flag, interrupt, and
external bus pins have dual, multiplexed functionality. The
external bus pins are configured during
RESET
only, while
serial port pins are software configurable during program execu-
tion. Flag and interrupt functionality is retained concurrently on
multiplexed pins. In cases where pin functionality is reconfigurable,
the default state is shown in plain text; alternate functionality is
shown in italics. See Pin Function Descriptions.
Memory Interface Pins
The AD73460 processor can be used in one of two modes, Full
Memory Mode, which allows BDMA operation with full exter-
nal overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capa-
bilities. The operating mode is determined by the state of the
Mode C pin during
RESET
and cannot be changed while the
processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
相关PDF资料 |
PDF描述 |
|---|---|
| AD73460BB-40 | Six-Input Channel Analog Front End |
| AD7346B | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD5011 | M5100-033-0008 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73460BB-40 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD73460BB-80 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD7346ASTZ | 制造商:Analog Devices 功能描述: |
| AD7346ASTZ-RL | 功能描述:IC ANALOG FRONT END 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD7346B | 制造商:AD 制造商全称:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
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