REV. 0
–5–
AD73460
SPECIFICATIONS
Parameter
Test Conditions
Min
Typ
Max
Unit
DSP SECTION
V
IH
Hi-Level Input Voltage
1, 2
V
IH
Hi-Level CLKIN Voltage
V
IL
Lo-Level Input Voltage
1, 3
V
OH
Hi-Level Output Voltage
1, 4, 5
@ V
DD
= max
@ V
DD
= max
@ V
DD
= min
@ V
DD
= min, I
OH
=
–
0.5 mA
@ V
DD
= min, I
OH
=
–
100
μ
A
6
@ V
DD
= min, I
OL
= 2 mA
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
8
@ V
DD
= max, V
IN
= 0 V
8
@ V
DD
= 3.3 V
t
CK
= 19 ns
10
t
CK
= 25 ns
10
t
CK
= 30 ns
10
@ V
DD
= 3.3 V, T
AMB
= 25
°
C
t
CK
= 19 ns
10
t
CK
= 25 ns
10
t
CK
= 30 ns
10
@ V
IN
= 2.5 V, f
IN
= 1.0 MHz, T
AMB
= 25
°
C
@ V
IN
= 2.5 V, f
IN
= 1.0 MHz, T
AMB
= 25
°
C
2.0
2.2
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
0.8
2.4
V
DD
–
0.3
V
OL
I
IH
I
IL
I
OZH
Three-State Leakage Current
7
I
OZL
Three-State Leakage Current
7
I
DD
Supply Current (Idle)
9
Lo-Level Output Voltage
1, 4, 5
Hi-Level Input Current
3
Lo-Level Input Current
3
0.4
10
10
10
10
14
12
10
mA
mA
mA
I
DD
Supply Current (Dynamic)
11
54
43
37
mA
mA
mA
pF
pF
C
I
C
O
Input Pin Capacitance
3, 6, 12
Output Pin Capacitance
6, 7, 12, 13
8
8
NOTES
Bidirectional pins: D0
–
D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1
–
A13, PF0
–
PF7.
2
Input only pins:
RESET
,
BR
, DR0, DR1,
PWD
.
3
Input only pins: CLKIN,
RESET
,
BR
, DR0, DR1,
PWD
.
4
Output pins:
BG
,
PMS
,
DMS
,
BMS
,
IOMS
,
CMS
,
RD
,
WR
,
PWDACK
, A0, DT0, DT1, CLKOUT, FL2
–
0,
BGH
.
5
Although specified for TTL outputs, all AD73460 outputs are CMOS-compatible and will drive to V
DD
and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0
–
A13, D0
–
D23,
PMS
,
DMS
,
BMS
,
IOMS
,
CMS
,
RD
,
WR
, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0
–
PF7.
8
0 V on
BR
.
9
Idle refers to AD73460 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD
or GND.
10
V
IN
= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11
I
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.
12
Applies to PBGA package type.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, f
MCLK
= 16.384 MHz, f
SAMP
= 64 kHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)