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参数资料
| 型号： | AD73460 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | 六输入通道模拟前端 |
| 文件页数： | 9/32页 |
| 文件大小： | 290K |
| 代理商： | AD73460 |
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AD73460
–9–
REV. 0
PIN FUNCTION DESCRIPTIONS
1
(continued)
Mnemonic
Function
WR
IRQ2
/
PF7
IRQL0/
PF6
IRQL1/
PF5
IRQE
/
PF4
Mode D/
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1
:0
FI
FO
PWD
PWDACK
FL0, FL1,
FL2
A13 to A0
D23 to D0
VDD and
GND
EZ-ICE Port
ERESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
EBR
EBG
(Output) Memory Write Enable Output
(Input) Edge- or Level-Sensitive Interrupt
(Input/Output) Request.
2
Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests
2
(Input/Output) Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests
2
(Input/Output) Programmable I/O Pin
(Input) Edge-Sensitive Interrupt Requests
2
(Input/Output) Programmable I/O Pin
(Input) Mode Select Input
—
Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input
—
Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input
—
Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input
—
Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Inputs) Clock or Quartz Crystal Input
(Output) Processor Clock Output
(Inputs/Outputs) Serial Port I/O Pins
(Inputs/Outputs) Serial Port I/O Pins
(Inputs) Edge- or Level-Sensitive Interrupts,
(Input) Flag In
3
(Output) Flag Out
3
(Input) Power-Down Control Input
(Output) Power-Down Control Output
(Outputs) Output Flags
(Output) Address Output Pins for Program, Data, Byte, and I/O Space
(Input/Output) Data I/O Pins for Program, Data, Byte, and I/O Space
Power and Ground
(Inputs/Outputs) For Emulation Use
NOTES
1
Refer to the ADSP-2185L data sheet for a detailed description of the DSP pins.
2
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
3
SPORT configuration determined by the DSP System Control Register. Software configurable.
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相关代理商/技术参数 |
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|---|---|
| AD73460BB-40 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD73460BB-80 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD7346ASTZ | 制造商:Analog Devices 功能描述: |
| AD7346ASTZ-RL | 功能描述:IC ANALOG FRONT END 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD7346B | 制造商:AD 制造商全称:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
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