- 您现在的位置：买卖IC网 > PDF目录373897 > AD73460 (Analog Devices, Inc.) Six-Input Channel Analog Front End PDF资料下载
参数资料
| 型号： | AD73460 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | 六输入通道模拟前端 |
| 文件页数： | 26/32页 |
| 文件大小： | 290K |
| 代理商： | AD73460 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页
REV. 0
AD73460
–26–
Program Memory (Host Mode)
allows access to all internal
memory. External overlay access is limited by a single exter-
nal address line (A0). External program execution is not
available in host mode due to a restricted data bus that is
only 16 bits wide.
Table XIX. PMOVLAY Bits
PMOVLAY Memory
A13
A12:0
0
1
Internal
External
Overlay 1
Not Applicable
0
Not Applicable
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
1
ACCESSIBLE WHEN
PMOVLAY = 2
0x2000
–
0x3FFF
2
EXTERNAL
MEMORY
ACCESSIBLE WHEN
PMOVLAY = 1
0x2000
–
0x3FFF
2
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000
–
0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
PM (MODE B = 0)
INTERNAL
MEMORY
0x2000
–
0x3FFF
8K INTERNAL
PMOVLAY = 0
3
OR
P8K EXTERNAL
0x3FFF
0x2000
0x1FFF
8K INTERNAL
0x0000
PROGRAM MEMORY
MODE B = 0
ADDRESS
8K INTERNAL
PMOVLAY = 0
3
8K EXTERNAL
PROGRAM MEMORY
MODE B = 1
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
ACCESSIBLE WHEN
PMOVLAY = 0
INTERNAL
MEMORY
EXTERNAL
0x2000
–
0x3FFF
0x0000
–
0x1FFF
2
PM (MODE B = 1)
1
RESERVED
ACCESSIBLE WHEN
PMOVLAY = 0
RESERVED
NOTES:
1
WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2
SEE TABLE III FOR PMOVLAY BITS
3
NOT ACCESSIBLE ON AD73422-40
Figure 13. Program Memory Map
DATA MEMORY
Data Memory (Full Memory Mode)
is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The AD73460-80 has 16K words on Data
Memory RAM on chip (the AD73460-40 has 8K words on Data
Memory RAM on chip), consisting of 16,352 user-accessible
locations in the case of the AD73460-80 (8,160 user-accessible
locations in the case of the AD73460-40) and 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All inter-
nal accesses complete in one cycle. Accesses to external memory
are timed using the wait states specified by the DWAIT register.
ACCESSIBLE WHEN
DMOVLAY = 2
ACCESSIBLE WHEN
DMOVLAY = 1
EXTERNAL
MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000
–
0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
INTERNAL
MEMORY
0x0000
–
0x1FFF
0x0000
–
0x1FFF
0x0000
–
0x1FFF
DATA MEMORY
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160
WORDS
0x3FFF
0x2000
0x1FFF
0x0000
DATA MEMORY
ADDRESS
8K INTERNAL
DMOVLAY = 0
OR
EXTERNAL 8K
DMOVLAY = 1, 2
0x3FE0
0x3FDF
Figure 14. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table XX.
Table XX. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
0
1
Internal
External
Overlay 1
Not Applicable
0
Not Applicable
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
1
I/O Space (Full Memory Mode)
The AD73460 supports an additional external memory space
called I/O space. This space is designed to support simple con-
nections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table XXI.
Table XXI. Wait States
Address Range
0x000
–
0x1FF
0x200
–
0x3FF
0x400
–
0x5FF
0x600
–
0x7FF
Wait State Register
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
Composite Memory Select (
CMS
)
The AD73460 has a programmable memory select signal that is
useful for generating memory select signals for memories mapped
to more than one space. The
CMS
signal is generated to have the
same timing as each of the individual memory select signals (
PMS
,
DMS
,
BMS
,
IOMS
) but can combine their functionality.
Each bit in the CMSSEL register, when set, causes the
CMS
signal to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both program
and data memory, set the
PMS
and
DMS
bits in the CMSSEL
register and use the
CMS
pin to drive the chip select of the
memory; use either
DMS
or
PMS
as the additional address bit.
相关PDF资料 |
PDF描述 |
|---|---|
| AD73460BB-40 | Six-Input Channel Analog Front End |
| AD7346B | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD5011 | M5100-033-0008 |
| AD5011B | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD73522 | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73460BB-40 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD73460BB-80 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:6-CHADC WITH DSP I.C. - Bulk |
| AD7346ASTZ | 制造商:Analog Devices 功能描述: |
| AD7346ASTZ-RL | 功能描述:IC ANALOG FRONT END 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD7346B | 制造商:AD 制造商全称:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
发布紧急采购，3分钟左右您将得到回复。