参数资料
型号: AD73460
厂商: Analog Devices, Inc.
英文描述: Six-Input Channel Analog Front End
中文描述: 六输入通道模拟前端
文件页数: 4/32页
文件大小: 290K
代理商: AD73460
REV. 0
–4–
AD73460
SPECIFICATIONS
Min
AD73460B
Parameter
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
IH
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
Three-State Leakage Current
POWER SUPPLIES
AVDD1, AVDD2
DVDD
I
DD8
V
DD
0.8
0
V
DD
0.8
10
10
V
V
μ
A
pF
V
DD
0.4
0
10
V
DD
0.4
+10
V
V
μ
A
|IOUT|
100
μ
A
|IOUT|
100
μ
A
3.0
3.0
3.6
3.6
V
V
See Table I
NOTES
1
Operating temperature range is as follows:
20
°
C to +85
°
C. Therefore, T
MIN
=
20
°
C and T
MAX
= +85
°
C.
2
Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC
s input impedance is inversely proportional to DMCLK and is approximated by: (4
×
10
11
)/DMCLK.
7
Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of
10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table I. AFE Section Current Summary (AVDD = DVDD = 3.3 V)
Total
Current
(Max)
MCLK
ON
Conditions
SE
Comments
REFCAP Only On
REFCAP and
REFOUT Only On
All Sections On
All Sections Off
All Sections Off
1.0
0
No
REFOUT Disabled
4.5
26.5
1.5
0.1
0
1
0
0
No
Yes
Yes
No
REFOUT Enabled
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V,
f
MCLK
= 16.384 MHz, f
SAMP
= 64 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
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