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| 型号： | AD7851KRZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 333KSPS 24-SOIC |
| 标准包装： | 31 |
| 位数： | 14 |
| 采样率（每秒）： | 333k |
| 数据接口： | 8051，QSPI?，串行，SPI? µP |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极；1 个伪差分，双极 |
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AD7851
–22–
REV. B
SYSTEM OFFSET
CALIBRATION
SYS OFFSET
VREF – 1LSB
AGND
MAX SYSTEM OFFSET
IS ±5% OF VREF
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
ANALOG
INPUT
RANGE
VREF – 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS ±5% OF VREF
VREF + SYS OFFSET
Figure 28. System Offset Calibration
Figure 29 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
SYSTEM GAIN
CALIBRATION
VREF – 1LSB
AGND
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
ANALOG
INPUT
RANGE
VREF – 1LSB
ANALOG
INPUT
RANGE
AGND
SYS FULL S.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
Figure 29. System Gain Calibration
Finally in Figure 30 both the system offset and gain are accounted
for by the system offset followed by a system gain calibration.
First the analog input range is shifted upwards by the positive
system offset and then the analog input range is adjusted at the
top end to account for the system full scale.
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATION
SYS OFFSET
VREF – 1LSB
AGND
MAX SYSTEM OFFSET
IS ±5% OF VREF
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
ANALOG
INPUT
RANGE
VREF – 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS ±5% OF VREF
VREF + SYS OFFSET
SYS F.S.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM VREF
SYS F.S.
Figure 30. System (Gain + Offset) Calibration
Self-Calibration Timing
Figure 27 shows the timing for a full self-calibration. Here the
BUSY line stays high for the full length of the self-calibration. A
self-calibration is initiated by bringing the
CAL pin low (which
initiates an internal reset) and then high again or by writing to
the control register and setting the STCAL bit to 1 (note that if
the part is in a power-down mode, the
CAL pulse width must
take account of the power-up time). The BUSY line is triggered
high from the rising edge of
CAL (or the end of the write to the
control register if calibration is initiated in the software), and
BUSY will go low when the full self-calibration is complete after
a time tCAL.
t1 = 100ns MIN,
t15 = 2.5 tCLKIN MAX,
tCAL = 250026 tCLKIN
CAL (I/P)
BUSY (O/P)
t1
t15
tCAL
Figure 27. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset, and self-gain calibrations,
the BUSY line will be triggered high by the rising edge of the
CAL signal (or the end of the write to the control register if cali-
bration is initiated in the software) and will stay high for the full
duration of the self-calibration. The length of time that the BUSY
is high will depend on the type of self-calibration that is initiated.
Typical figures are given in Table VIII. The timing diagrams for
the other self-calibration options will be similar to Figure 27.
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7851 as well as calibrate the errors of the
AD7851 itself. The maximum calibration range for the system
offset errors is
±5% of V
REF and for the system gain errors is
±2.5% of V
REF. This means that the maximum allowable system
offset voltage applied between the AIN(+) and AIN(–) pins for
the calibration to adjust out this error is
±0.05 × V
REF (that is,
the AIN(+) can be 0.05
× V
REF above AIN(–) or 0.05
× V
REF
below AIN(–)). For the system gain error, the maximum allow-
able system full-scale voltage, in unipolar mode, that can be
applied between AIN(+) and AIN(–) for the calibration to
adjust out this error is VREF
± 0.025 × VREF (that is, the AIN(+)
can be VREF + 0.025
× V
REF above AIN(–) or VREF – 0.025
×
VREF above AIN(–)). If the system offset or system gain errors
are outside the ranges mentioned, the system calibration algo-
rithm will reduce the errors as much as the trim range allows.
Figures 28, 29, and 30 illustrate why a specific type of system
calibration might be used. Figure 28 shows a system offset
calibration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
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