参数资料
型号: AD7851KRZ
厂商: Analog Devices Inc
文件页数: 33/36页
文件大小: 0K
描述: IC ADC 14BIT SRL 333KSPS 24-SOIC
标准包装: 31
位数: 14
采样率(每秒): 333k
数据接口: 8051,QSPI?,串行,SPI? µP
转换器数目: 2
功率耗散(最大): 89.25mW
电压电源: 模拟和数字
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 管件
输入数目和类型: 1 个伪差分,单极;1 个伪差分,双极
AD7851
–6–
REV. B
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in
Interface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least a 330 ns acquisition time must be allowed (the time
from the falling edge of BUSY to the next rising edge of
CONVST) before the next conversion begins to ensure that the
part is settled to the 14-bit level. If the user does not want to
provide the
CONVST signal, the conversion can be initiated in
software by writing to the control register.
1.6mA
2.1V
200A
CL
50pF
TO
OUTPUT
PIN
IOL
IOH
Figure 1. Load Circuit for Digital Output Timing
Specifications
DB15
DB0
DB11
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
6
t
9
t
10
15
6
16
t
12
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
THREE-STATE
DB15
t
CONVERT
t
CONVERT = 3.25s MAX, t1 = 100ns MIN,
t
5 = 30ns MAX, t7 = 30ns MIN
t
1
t
6
t
7
Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
SYNC ( O/P)
SCLK (O/P)
t
4
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
12
t
9
t
10
15
6
16
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
DB15
DB0
THREE-STATE
DB11
THREE-STATE
DB15
t
CONVERT
t
CONVERT = 3.25s MAX, t1 = 100ns MIN,
t
5 = 30ns MAX, t7 = 30ns MIN
t
1
t
6
t
7
Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
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