参数资料
| 型号： | AD9146BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/56页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SRL DUAL 48LFCSP |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| 设置时间： | 20ns |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-WQ（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 1.23G |
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AD9146
Data Sheet
Rev. A | Page 28 of 56
LVDS INPUT DATA PORTS
The AD9146 has one LVDS data port that receives data for both
the I and Q transmit paths. The device can accept data in byte
and nibble formats. In byte and nibble modes, the data is sent
over 8-bit and 4-bit LVDS data buses, respectively. The pin
assignments of the bus in each mode are shown in Table 12.
Table 12. Data Bit Pair Assignments for Data Input Modes
Mode
MSB to LSB
Byte
D7, D6, D5, D4, D3, D2, D1, D0
Nibble1
D5, D4, D3, D2
1
In nibble mode, the unused pins can be left floating.
The data is accompanied by DCI and FRAME signals. The DCI
signal is a reference bit that is used to generate a double data rate
(DDR) clock. The FRAME signal is required for controlling to
which DAC the data is sent. All of the interface signals can be time
aligned, so there is a maximum skew requirement on the bus. In
some cases, it is best to delay the DCI signal for optimum timing.
BYTE INTERFACE MODE
In byte mode, the DCI signal is a reference bit used to generate
the data sampling clock and should be time aligned with the data.
The most significant byte of the data should correspond to DCI
high, and the least significant byte of the data should correspond to
DCI low. The FRAME signal indicates to which DAC the data
is sent. When FRAME is high, data is sent to the I DAC; when
FRAME is low, data is sent to the Q DAC. The complete timing
diagram is shown in Figure 30.
NIBBLE INTERFACE MODE
In nibble mode, the DCI signal is a reference bit used to generate
the data sampling clock and should be time aligned with the data.
The FRAME signal indicates to which DAC the data is sent.
When FRAME is high, data is sent to the I DAC; when FRAME
is low, data is sent to the Q DAC. All four nibbles must be written
to the device for proper operation. For 12-bit resolution devices,
the data in the fourth nibble acts as a placeholder for the data
framing structure. The complete timing diagram is shown in
FIFO OPERATION
The AD9146 contains a 2-channel, 16-bit wide, eight-word deep
FIFO designed to relax the timing relationship between the data
arriving at the DAC input ports and the internal DAC data rate
clock. The FIFO acts as a buffer that absorbs timing variations
between the data source and the DAC, such as the clock-to-data
variation of an FPGA or ASIC, which significantly increases the
timing budget of the interface.
Figure 32 shows the block diagram of the datapath through the
FIFO. The data is latched into the device, is formatted, and is
then written into the FIFO register determined by the FIFO write
pointer. The value of the write pointer is incremented every time a
new word is loaded into the FIFO. Meanwhile, data is read from
the FIFO register determined by the read pointer and fed into
the digital datapath. The value of the read pointer is incremented
every time data is read into the datapath from the FIFO. The FIFO
pointers are incremented at the data rate (DACCLK rate divided by
the interpolation ratio).
Valid data is transmitted through the FIFO as long as the
FIFO does not overflow or become empty. An overflow or
empty condition of the FIFO occurs when the write pointer and
read pointer point to the same FIFO location. This simultan-
eous access of data leads to unreliable data transfer through
the FIFO and must be avoided.
DCI
DATA[15:0]
FRAME
Q0LSB
I1MSB
I1LSB
Q1MSB
Q1LSB
I2MSB
I2LSB
Q2MSB Q2LSB
09691-
037
Figure 30. Timing Diagram for Byte Mode
DCI
DATA[15:0]
FRAME
Q0N0
I1N3
I1N2
I1N1
I1N0
Q1N3
Q1N2
Q1N1
Q1N0
I2N3
09691-
038
Figure 31. Timing Diagram for Nibble Mode
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9146BCPZRL | 功能描述:IC DAC 16BIT SRL DUAL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9146-EBZ | 制造商:Analog Devices 功能描述:16 BIT DUAL SIGNAL PROC DAC EB - Boxed Product (Development Kits) |
| AD9146-M5375-EBZ | 功能描述:BOARD EVAL FOR AD9146 DAC RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148ARUZ | 制造商:Analog Devices 功能描述:- Rail/Tube |
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