参数资料
| 型号： | AD9146BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 41/56页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SRL DUAL 48LFCSP |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| 设置时间： | 20ns |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-WQ（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 1.23G |
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AD9146
Data Sheet
Rev. A | Page 46 of 56
REFCLKP(1)/
REFCLKN(1)
REFCLKP(2)/
REFCLKN(2)
DCIP(2)/
DCIN(2)
FRAMEP(2)/
FRAMEN(2)
tSKEW
tSDCI
tHDCI
09691-
070
Figure 63. Timing Diagram Required for Synchronizing Devices
DACCLKP/
DACCLKN
FRAMEP/
FRAMEN
REFCLKP/
REFCLKN
DCIP/
DCIN
IOUT1P/
IOUT1N
DCIP/
DCIN
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAMEP/
FRAMEN
IOUT2P/
IOUT2N
SAMPLE
RATE CLOCK
LOW SKEW
CLOCK DRIVER
SYNC
CLOCK
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
FPGA
09691-
071
Figure 64. Typical Circuit Diagram for Synchronizing Devices to a System Clock
To maintain synchronization, the skew between the REFCLK
signals of the devices must be less than tSKEW ns. When resetting
the FIFO, the FRAME signal must be held high for the time
interval required to write two complete input data words. A
timing diagram of the input signals is shown in Figure 63.
Figure 63 shows a REFCLK frequency equal to the data rate.
Although this is the most common situation, it is not strictly
required for proper synchronization. Any REFCLK frequency
that satisfies the following equation is acceptable. (This equation
is valid only when the PLL is used because only data rate mode
is available with the PLL on.)
fSYNC_I = fDACCLK/2N and fSYNC_I ≤ fDATA
where N = 0, 1, 2, or 3.
As an example, a configuration with 4× interpolation and clock
frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, fDATA =
200 MHz, and fSYNC_I = 100 MHz is a viable solution.
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock, a separate
REFCLK input signal is required for synchronization. To syn-
chronize devices, the DACCLK signal and the REFCLK signal
must be distributed with low skew to all the devices being syn-
chronized. If the devices need to be synchronized to a master
clock, use the master clock directly for generating the REFCLK
input (see Figure 64).
DATA RATE MODE SYNCHRONIZATION
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in data rate mode.
The procedure assumes that the DACCLK and REFCLK signals
are applied to all the devices. The following procedure must be
carried out on each individual device.
Procedure for Data Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
Configure the AD9146 for data rate, periodic synchronization
by writing 0xC8 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
Additional Synchronization Features section).
Read the sync locked bit (Register 0x12, Bit 6) to verify that the
device is back-end synchronized. A high level on this bit indicates
that the clocks are running with a constant and known phase
relative to the synchronization signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9146BCPZRL | 功能描述:IC DAC 16BIT SRL DUAL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9146-EBZ | 制造商:Analog Devices 功能描述:16 BIT DUAL SIGNAL PROC DAC EB - Boxed Product (Development Kits) |
| AD9146-M5375-EBZ | 功能描述:BOARD EVAL FOR AD9146 DAC RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148ARUZ | 制造商:Analog Devices 功能描述:- Rail/Tube |
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