Data Sheet
AD9517-3
Rev. E | Page 19 of 80
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
15
O
3.3 V CMOS
SDO
Serial Control Port. Unidirectional serial data output.
16
I/O
3.3 V CMOS
SDIO
Serial Control Port. Bidirectional serial data input/output and unidirectional serial
data input.
17
I
3.3 V CMOS
RESET
Chip Reset, Active Low. This pin has an internal 30 k pull-up resistor.
18
I
3.3 V CMOS
PD
Chip Power Down, Active Low. This pin has an internal 30 k pull-up resistor.
21, 40
I
Power
VS_LVPECL
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
42
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
41
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
39
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
38
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
19
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
20
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
22
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
23
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
35
O
LVDS or
CMOS
OUT4 (OUT4A)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
34
O
LVDS or
CMOS
OUT4 (OUT4B)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
33
O
LVDS or
CMOS
OUT5 (OUT5A)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
32
O
LVDS or
CMOS
OUT5 (OUT5B)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
26
O
LVDS or
CMOS
OUT6 (OUT6A)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
27
O
LVDS or
CMOS
OUT6 (OUT6B)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
28
O
LVDS or
CMOS
OUT7 (OUT7A)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
29
O
LVDS or
CMOS
OUT7 (OUT7B)
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
44
O
Current set
resistor
RSET
Resistor connected here sets internal bias currents. Nominal value = 4.12 k.
46
O
Current set
resistor
CPRSET
Resistor connected here sets CP current range. Nominal value = 5.1 k.
47
I
Reference
input
REFIN (REF2)
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
48
I
Reference
input
REFIN (REF1)
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.
EPAD
GND
Ground. The external paddle on the bottom of the package must be connected to
ground for proper operation.