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参数资料
| 型号： | AD9520-1BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9520-1/PCBZ-ND - BOARD EVAL FOR AD9520-1 |
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Data Sheet
AD9520-1
Rev. A | Page 37 of 80
Prescaler
The prescaler of the AD9520 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3,
4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 54, Register 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
When operating the AD9520 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in FD Mode 1, FD Mode 2,
or FD Mode 3, the A counter is not used (A = 0; the divide is a
fixed divide of P = 2, 4, 8, 16, or 32) and the equation simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
By using combinations of DM and FD modes, the AD9520 can
achieve values of N from 1 to 262,175.
Table 29 shows how a 10 MHz reference input can be locked to
any integer multiple of N.
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode of P = 2 with B = 6; use the dual modulus mode of
2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with
A = 0, B = 3.
A and B Counters
The B counter must be ≥3 or bypassed, and unlike the R
counter, A = 0 is actually zero.
When the prescaler is in dual modulus mode, the A counter
must be equal to or less than the B counter.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) that is
specified in Table 2. This is the prescaler input frequency (VCO or
CLK) divided by P. For example, a dual modulus mode of P = 8/9
is not allowed if the VCO frequency is greater than 2400 MHz
because the frequency going to the A/B counter is too high.
When the AD9520 B counter is bypassed (B = 1), the A counter
should be set to zero, and the overall resulting divide is equal to
the prescaler setting, P. The possible divide ratios in this mode
are 1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an
external VCO/VCXO is used because the frequency range of the
internal VCO requires an overall feedback divider greater than 32.
Although manual reset is not normally required, the A/B counters
have their own reset bit. Alternatively, the A and B counters can be
reset using the shared reset bit of the R, A, and B counters. Note
that these reset bits are not self-clearing.
R, A, and B Counters—SYNC Pin Reset
The R, A, and B counters can be reset simultaneously through the
SYNC pin. This function is controlled by Register 0x019[7:6] (see
Table 54). The SYNC pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Table 2 and Table 54.
Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
fREF (MHz)
R
P
A
B
N
fVCO (MHz)
Mode
Description
10
1
X1
1
10
FD
P = 1, B = 1 (A and B counters are bypassed).
10
1
2
X1
1
2
20
FD
P = 2, B = 1 (A and B counters are bypassed).
10
1
X1
3
30
FD
A counter is bypassed.
10
1
X1
4
40
FD
A counter is bypassed.
10
1
X1
5
50
FD
A counter is bypassed.
10
1
2
X1
3
6
60
FD
A counter is bypassed.
10
1
2
0
3
6
60
DM
10
1
2
1
3
7
70
DM
Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.
If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz
to 300 MHz, use P = 1 and N = 7 or 11, respectively.
10
1
2
3
8
80
DM
10
1
2
1
4
9
90
DM
10
1
8
6
18
150
1500
DM
10
1
8
7
18
151
1510
DM
10
1
16
7
9
151
1510
DM
10
32
6
47
1510
DM
10
1
8
0
25
200
2000
DM
10
1
16
0
15
240
2400
DM
10
32
0
75
2400
DM
.
1
X = don’t care
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| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9520-2/PCBZ | 功能描述:BOARD EVAL AD9520-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9520-2BCPZ | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-2BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-3 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO |
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