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参数资料
| 型号： | AD9520-1BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9520-1/PCBZ-ND - BOARD EVAL FOR AD9520-1 |
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AD9520-1
Data Sheet
Rev. A | Page 40 of 80
A flowchart of the automatic/internal holdover function
operation is shown in Figure 47.
NO
YES
PLL ENABLED
DLD == LOW
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
HIGH IMPEDANCE
CHARGE PUMP
REFERENCE
EDGE AT PFD?
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
DLD == HIGH
YES
07
21
4
-06
9
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK, AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
REG 0x01D[3]: LD PIN COMPARATOR ENABLE.
0b = DISABLE; 1b = ENABLE. WHEN DISABLED,
THE HOLDOVER FUNCTION ALWAYS SENSES
THE LD PIN AS HIGH.
CHARGE PUMP IS MADE HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH IMPEDANCE
UNTIL THE REFERENCE RETURNS.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
Figure 47. Flowchart of Automatic/Internal Holdover Mode
The following registers affect the automatic/internal holdover
function:
Register 0x018[6:5]—lock detect counter. This changes
how many consecutive PFD cycles with edges inside the
lock detect window are required for the DLD indicator to
indicate lock. This impacts the time required before the LD
pin can begin to charge as well as the delay from the end of a
holdover event until the holdover function can be reengaged.
Register 0x018[3]—disable digital lock detect. This bit
must be set to 0b to enable the DLD circuit. Automatic/
internal holdover does not operate correctly without the
DLD function enabled.
Register 0x01A[5:0]—lock detect pin control. Set these bits
to 000100b to program the current source lock detect mode
if using the LD pin comparator. Load the LD pin with
a capacitor of an appropriate value.
Register 0x01D[3]—LD pin comparator enable. 1b =
enable; 0b = disable. When disabled, the holdover function
always senses the LD pin as high.
Register 0x01D[1]—external holdover control.
Register 0x01D[0]—holdover enable. If holdover is
disabled, both external and automatic/ internal holdover
are disabled.
In the following example, automatic holdover is configured with
Automatic reference switchover, prefer REF1.
Digital lock detect: five PFD cycles, high range window.
Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL
registers):
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; digital lock detect window = high
range.
Register 0x018[3] = 1b; disable DLD normal operation.
Register 0x01A[5:0] = 000100b; program LD pin control to
current source lock detect mode.
Register 0x01C[4] = 1b; enable automatic switchover.
Register 0x01C[3] = 0b; prefer REF1.
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[1] = 0b; disable external holdover mode and
use automatic/internal holdover mode.
Register 0x01D[0] = 1b; enable holdover.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9520-2/PCBZ | 功能描述:BOARD EVAL AD9520-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9520-2BCPZ | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-2BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-3 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO |
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