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参数资料
| 型号： | AD9524/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9524 |
| 设计资源： | AD9524 Schematic AD9524 BOM AD9524 Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9524 |
| 主要属性： | USB 供电或外部电源 |
| 次要属性： | 状态 LED |
| 已供物品： | 板 |
| 配用： | AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP |
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Data Sheet
AD9524
Rev. E | Page 51 of 56
Address
Bits
Bit Name
Description
1
Tristate output
0x197
[7:0]
Channel divider, Bits[7:0] (LSB)
Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1
is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).
0x198
[7:2]
Divider phase
Divider initial phase after a sync is asserted relative to the divider input clock (from the
VCO divider output). LSB = of a period of the divider input clock.
Phase = 0: no phase offset.
Phase = 1: period offset, …
Phase = 63: 31 period offset.
[1:0]
Channel divider, Bits[9:8] (MSB)
10-bit channel divider, Bits[9:8] (MSB).
Table 53. PLL1 Output Control (PLL1_OUT, Pin 46)
Address
Bits
Bit Name
Description
0x1BA
[7:5]
Reserved
4
PLL1 output CMOS driver
strength
CMOS driver strength
1: weak
0: strong
[3:0]
PLL1 output divider
0000: divide-by-1
0001: divide-by-2 (default)
0010: divide-by-4
0100: divide-by-8
1000: divide-by-16
No other inputs permitted
Table 54. PLL1 Output Channel Control
Address
Bits
Bit Name
Description
0x1BB
7
PLL1 output driver power-down
[6:2]
Reserved
1
Route VCXO clock to
Channel 1 divider input
1: channel uses VCXO clock. Routes VCXO clock to divider input
0: channel uses VCO divider output clock
0
Route VCXO clock to
Channel 0 divider input
1: channel uses VCXO clock. Routes VCXO clock to divider input
0: channel uses VCO divider output clock
Readback (Address 0x22C to Address 0x22D)
Table 55. Readback Registers (Readback 0 and Readback 1)
Address
Bits
Bit Name
Description
0x22C
7
Status PLL2 reference clock
1: OK
0: off/clocks are missing
6
Status PLL1 feedback clock
1: OK
0: off/clocks are missing
5
Status VCXO
1: OK
0: off/clocks are missing
4
Status REF_TEST
1: OK
0: off/clocks are missing
3
Status REFB
1: OK
0: off/clocks are missing
2
Status REFA
1: OK
0: off/clocks are missing
1
Lock detect PLL2
1: locked
0: unlocked
0
Lock detect PLL1
1: locked
0: unlocked
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9525 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Jitter Clock Generator with Eight LVPECL Outputs |
| AD9525/PCBZ | 功能描述:时钟和定时器开发工具 Evaluation kit 2950MHz VCO installed RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| AD9525/PCBZ-VCO | 功能描述:时钟和定时器开发工具 Evaluation kit CRO29508 VCO installed RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| AD9525BCPZ | 功能描述:时钟发生器及支持产品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| AD9525BCPZ-REEL7 | 功能描述:时钟发生器及支持产品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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