参数资料
| 型号： | AD9577BCPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 1/44页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN PLL DUAL 40LFCSP |
| 标准包装： | 2,500 |
| 系列： | PCI Express® (PCIe) |
| 类型： | 扇出缓冲器（分配），网络时钟发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，PCI Express（PCIe），SONET/SDH |
| 输入： | 时钟，晶体 |
| 输出： | LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 637.5MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 带卷 (TR) |
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Clock Generator with Dual PLLs,
Spread Spectrum, and Margining
Data Sheet
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2011 Analog Devices, Inc. All rights reserved.
FEATURES
Fully integrated dual PLL/VCO cores
1 integer-N and 1 fractional-N PLL
Continuous frequency coverage from 11.2 MHz to 200 MHz
Most frequencies from 200 MHz to 637.5 MHz available
PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical
PLL2 phase jitter (12 kHz to 20 MHz)
Integer-N mode: 470 fs rms typical
Fractional-N mode: 660 fs rms typical
Input crystal or reference clock frequency
Optional reference frequency divide-by-2
I2C programmable output frequencies
Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks
1 CMOS buffered reference clock output
Spread spectrum: downspread [0, 0.5]%
2 pin-controlled frequency maps: margining
Integrated loop filters
Space saving, 6 mm × 6 mm, 40-lead LFCSP package
1.02 W power dissipation (LVDS operation)
1.235 W power dissipation (LVPECL operation)
3.3 V operation
APPLICATIONS
Low jitter, low phase noise multioutput clock generator for
data communications applications including Ethernet,
Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN,
ADC/DAC, and digital video
Spread spectrum clocking
GENERAL DESCRIPTION
The AD9577 provides a multioutput clock generator function,
along with two on-chip phase-locked loop cores, PLL1 and PLL2,
optimized for network clocking applications. The PLL designs
are based on the Analog Devices, Inc., proven portfolio of high
performance, low jitter frequency synthesizers to maximize
network performance. The PLLs have I2C programmable output
frequencies and formats. The fractional-N PLL can support
spread spectrum clocking for reduced EMI radiated peak power.
Both PLLs can support frequency margining. Other applications
with demanding phase noise and jitter requirements can benefit
from this part.
The first integer-N PLL section (PLL1) consists of a low noise phase
frequency detector (PFD), a precision charge pump (CP), a low
phase noise voltage controlled oscillator (VCO), a programmable
FUNCTIONAL BLOCK DIAGRAM
XTAL
OSC
REFCLK
XT1
XT2
MARGIN
REFSEL
CMOS
AD9577
DIVIDE
1 OR 2
VCO
2.15GHz
TO
2.55GHz
P
F
D/
CP
TH
IR
D
O
RDE
R
L
P
F
LDO
FEEDBACK
DIVIDER
LVPECL/LVDS
REFOUT
OR 2 × CMOS
DI
V
IDE
RS
LVPECL/LVDS
OR 2 × CMOS
DI
V
IDE
R
S
f PF
D
PLL1
VCO
2.15GHz
TO
2.55GHz
P
F
D/
CP
TH
IR
D
O
RDE
R
L
P
F
LDO
FEEDBACK
DIVIDER
LVPECL/LVDS
OR 2 × CMOS
DI
V
IDE
R
S
LVPECL/LVDS
OR 2 × CMOS
D
IV
IDE
RS
PLL2
SCL
SDA
I2C
CONTROL
SSCG
MAX_BW
SPREAD SPECTRUM,
SDM
09
28
4-
0
01
Figure 1.
feedback divider, and two independently programmable output
dividers. By connecting an external crystal or applying a reference
clock to the REFCLK pin, frequencies of up to 637.5 MHz can
be synchronized to the input reference. Each output divider and
feedback divider ratio is I2C programmed for the required
output rates.
A second fractional-N PLL (PLL2) with a programmable modulus
allows VCO frequencies that are fractional multiples of the
reference frequency to be synthesized. Each output divider
and feedback divider ratio can be programmed for the required
output rates, up to 637.5 MHz. This fractional-N PLL can also
operate in integer-N mode for the lowest jitter.
Up to four differential output clock signals can be configured
as either LVPECL or LVDS signaling formats. Alternatively,
the outputs can be configured for up to eight CMOS outputs.
Combinations of these formats are supported. No external loop
filter components are required, thus conserving valuable design
time and board space. The AD9577 is available in a 40-lead, 6 mm ×
6 mm LFCSP package and can operate from a single 3.3 V supply.
The operating temperature range is 40°C to +85°C.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9577-EVALZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Clock Generator with Dual PLLs |
| AD9578BCPZ | 功能描述:IC PLL CLOCK GEN 20MHZ 48LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 类型:* PLL:带旁路 输入:LVCMOS，LVDS，LVPECL，晶体 输出:HCSL，LVCMOS，LVDS，LVPECL 电路数:1 比率 - 输入:输出:2：5 差分 - 输入:输出:是/是 频率 - 最大值:919MHz 分频器/倍频器:是/无 电压 - 电源:2.375 V ~ 3.63 V 工作温度:-25°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘，CSP 供应商器件封装:48-LFCSP-VQ（7x7） 标准包装:1 |
| AD9578BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 20MHZ 48LFCSP 制造商:analog devices inc. 系列:- 包装:剪切带（CT） 零件状态:有效 类型:* PLL:带旁路 输入:LVCMOS，LVDS，LVPECL，晶体 输出:HCSL，LVCMOS，LVDS，LVPECL 电路数:1 比率 - 输入:输出:2：5 差分 - 输入:输出:是/是 频率 - 最大值:919MHz 分频器/倍频器:是/无 电压 - 电源:2.375 V ~ 3.63 V 工作温度:-25°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘，CSP 供应商器件封装:48-LFCSP-VQ（7x7） 标准包装:1 |
| AD95S08KAC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|DOUBLER|HALF-CNTLD|POSITIVE|15V V(RRM)|95A I(T) |
| AD95S08KAF | 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|DOUBLER|HALF-CNTLD|POSITIVE|15V V(RRM)|95A I(T) |
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