参数资料
| 型号： | ADATE207BBPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC TIMING FORMATTER QUAD 256BGA |
| 标准包装： | 1 |
| 类型： | 四针定时格式器 |
| PLL： | 是 |
| 主要目的： | 自动测试设备 |
| 电路数： | 4 |
| 频率 - 最大： | 100MHz |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA 裸露焊盘 |
| 供应商设备封装： | 256-BGA（27x27） |
| 包装： | 托盘 |
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ADATE207
Rev. 0 | Page 24 of 36
Name:
Dynamic Configuration
Address:
0x04
Type:
Read/Write
Table 18. Dynamic Configuration
Position
Description
Reset State
Bits[15:05]
Not Used.
0x000
Bit 04
Edge Generation Enable.
Low turns off the channel’s edge delay generators.
High turns on the channel’s edge delay generators.
Bit 03
T0 and C0 Select.
0
Low selects T0 as the pattern cycle clock for the edge delay generators.
High selects C0 as the pattern cycle clock for the edge delay generators.
When in C0 mode, compare events are illegal and treated as no action.
Bit 02
Fail Mask.
0
High statically disables channel failures by the Accumulated Fail registers and the fail counter.
Low allows use of the pattern fail mask signals.
Bit 01
Low Jitter Clock Enable.
0
High statically enables the low jitter clock input onto the channel’s drive data output.
Low disables the low jitter clock for the channel. This feature only applies to Channel 2 and
Channel 3.
The low jitter clock signal is not available on Channel 0 and Channel 1.
Bit 00
Fail Counter Increment.
0
Writing a 1 to this bit creates a pulse to increment the fail counter.
Writing a 0 has no effect.
Waveform and Calibration Memory Addresses
To gain access to the timing set memory, the timing set memory address must be programmed to the desired address.
Name:
Waveform/Calibration Memory Address
Address:
0x05
Type:
Read/Write
Table 19. Waveform/Calibration Memory Address
Position
Description
Reset State
Bits[15:10]
Not Used.
0x00
Bits[09:08]
Waveform Memory Address Auto-Increment. Sets the address to auto-increment on a read from, or
write to, the following registers, based on the value programmed into this field:
0
0 = Waveform D0 Course Delay or Calibration Memory D0.
1 = Waveform D1 Course Delay or Calibration Memory D1.
2 = Waveform D2 Course Delay or Calibration Memory D2.
3 = Waveform D3 Course Delay or Calibration Memory D3.
Bits[07:00]
Waveform Memory Programming Address. Sets the address into either the waveform memory or
calibration memory.
0
Writing to, or reading from, the Waveform Dx course delay, Waveform Dx vernier delay and action,
or calibration memory data registers uses the address value programmed into this register.
Reads of this register reflect the current state of the auto-incremented address.
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