参数资料
| 型号： | ADATE207BBPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/36页 |
| 文件大小： | 0K |
| 描述： | IC TIMING FORMATTER QUAD 256BGA |
| 标准包装： | 1 |
| 类型： | 四针定时格式器 |
| PLL： | 是 |
| 主要目的： | 自动测试设备 |
| 电路数： | 4 |
| 频率 - 最大： | 100MHz |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA 裸露焊盘 |
| 供应商设备封装： | 256-BGA（27x27） |
| 包装： | 托盘 |
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ADATE207
Rev. 0 | Page 16 of 36
After the power and MCLK inputs are stable, the device must be
reset using the hard reset and error reset bits. The soft reset can
be used to initialize registers at any time and does not reset the
PLL or FIFOs.
There are six rules of reset.
Rule 1—on power up, keep the hard reset pin (RESET_B)
asserted.
Rule 2—if MCLK is unstable, keep the hard reset pin
(RESET_B) asserted.
Rule 3—after MCLK is stable, keep the hard reset pin
(RESET_B) asserted for at least 20 μs.
Rule 4—after the 20 μs of Rule 3 has elapsed, assert the error
reset bit (Bit 03 in Register 0x19).
Rule 5—the hard reset signal (RESET_B) can be asserted
asynchronously to MCLK, but upon deassertion, must make
setup and hold requirements upon the MCLK.
Rule 6—the minimum pulse width of RESET_B must be at least
three MCLK periods.
Table 11. Comparison Between Normal Mode and Clock Generation Mode
Normal Mode (CLKGEN_MD_EN=0)
Clock Generator Mode(CLKGEN_MD_EN=1)
Period Start
A single signal for all four channels, I_PER_EARLY_T0EN.
Four signals, one per channel; PAT_MASK[N] operates
as a period start signal for channel N.
Waveform
Memory Selection
Each channel N is selected via the I_PAT_PATDATA_N vector
every rising edge of I_MCLK.
Waveform memory location is fixed at Address 0.
Input Delay
A single vector adjust input delay for all channels,
INPUT_DELAY.
Four vectors are available, one per channel. For each
Channel N, PAT_PATDATA_N operates as
INPUT_DELAY for Channel N.
Fail Masking
Edge N for all channels can mask the fail operation every
rising edge of I_MCLK via PAT_MASK[N].
No masking of fail operations is available.
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