参数资料
型号: ADAU1461WBCPZ-R7
厂商: Analog Devices Inc
文件页数: 51/88页
文件大小: 0K
描述: IC SIGMADSP 24BIT 96KHZ PLL 32
标准包装: 1,500
系列: SigmaDSP®
类型: 音频处理器
应用: 车载音频
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ
包装: 带卷 (TR)
ADAU1461
Rev. 0 | Page 55 of 88
R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D)
This register controls the gain boost of the right channel differential PGA input and the gain for the right channel auxiliary input in the
record path. The right channel record mixer is referred to as Mixer 2.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
RDBOOST[1:0]
MX2AUXG[2:0]
Table 39. Record Mixer Right (Mixer 2) Control 1 Register
Bits
Bit Name
Description
[4:3]
RDBOOST[1:0]
Right channel differential PGA input gain boost, input to Mixer 2. The right differential input uses the RINP
(positive signal) and RINN (negative signal) pins.
Setting
Gain Boost
00
Mute (default)
01
0 dB
10
20 dB
11
Reserved
[2:0]
MX2AUXG[2:0]
Right single-ended auxiliary input gain from the RAUX pin in the record path, input to Mixer 2.
Setting
Auxiliary Input Gain
000
Mute (default)
001
12 dB
010
9 dB
011
6 dB
100
3 dB
101
0 dB
110
3 dB
111
6 dB
R8: Left Differential Input Volume Control, 16,398 (0x400E)
This register enables the differential path and sets the volume control for the left differential PGA input.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDVOL[5:0]
LDMUTE
LDEN
Table 40. Left Differential Input Volume Control Register
Bits
Bit Name
Description
[7:2]
LDVOL[5:0]
Left channel differential PGA input volume control. The left differential input uses the LINP (positive signal) and
LINN (negative signal) pins. Each step corresponds to a 0.75 dB increase in gain. See Table 90 for a complete list
of the volume settings.
Setting
Volume
000000
12 dB (default)
000001
11.25 dB
010000
0 dB
111110
34.5 dB
111111
35.25 dB
1
LDMUTE
Left differential input mute control.
0 = mute (default).
1 = unmute.
0
LDEN
Left differential PGA enable. When enabled, the LINP and LINN pins are used as a full differential pair. When
disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA.
0 = disabled (default).
1 = enabled.
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