参数资料
型号: ADAU1461WBCPZ-R7
厂商: Analog Devices Inc
文件页数: 80/88页
文件大小: 0K
描述: IC SIGMADSP 24BIT 96KHZ PLL 32
标准包装: 1,500
系列: SigmaDSP®
类型: 音频处理器
应用: 车载音频
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ
包装: 带卷 (TR)
ADAU1461
Rev. 0 | Page 81 of 88
R63: DSP Slew Modes, 16,631 (0x40F7)
The DSP slew modes register sets the slew source for each output. The slew source can be either the DSP (digital slew) or the codec (analog
slew). When these bits are set to Logic 0, the codec provides volume slew according to the ASLEW[1:0] bits in Register R34 (playback
pop/click suppression register, Address 0x4028). When these bits are set to Logic 1, the slew is provided and defined by the DSP program,
disabling the codec volume slew.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
MOSLW
ROSLW
LOSLW
RHPSLW
LHPSLW
Table 86. DSP Slew Modes Register
Bits
Bit Name
Description
4
MOSLW
Mono output slew generation.
0 = codec (default).
1 = DSP.
3
ROSLW
Line output right slew generation.
0 = codec (default).
1 = DSP.
2
LOSLW
Line output left slew generation.
0 = codec (default).
1 = DSP.
1
RHPSLW
Headphone right slew generation.
0 = codec (default).
1 = DSP.
0
LHPSLW
Headphone left slew generation.
0 = codec (default).
1 = DSP.
R64: Serial Port Sampling Rate, 16,632 (0x40F8)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SPSR[2:0]
Table 87. Serial Port Sampling Rate Register
Bits
Bit Name
Description
[2:0]
SPSR[2:0]
Serial port sampling rate. The serial port sampling rate is a ratio of the base sampling rate, fS. The base sampling
rate is determined by the operating frequency of the core clock. For most applications, the serial port sampling
rate should equal the converter sampling rate (set using the CONVSR[2:0] bits in Register R17) and the DSP sampling
rate (set using the DSPSR[3:0] bits in Register R57).
Setting
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
000
fS
48 kHz, base (default)
001
fS/6
8 kHz
010
fS/4
12 kHz
011
fS/3
16 kHz
100
fS/2
24 kHz
101
fS/1.5
32 kHz
110
fS/0.5
96 kHz
111
Reserved
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