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| 型号： | ADE7953ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 45/72页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PH 28LFCSP |
| 标准包装： | 1 |
| 输入阻抗： | 660 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.4V |
| 电流 - 电源： | 6.8mA |
| 电源电压： | 3 V ~ 3.6 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 28-LFCSP-WQ（5x5） |
| 包装： | 托盘 |
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? 1 ÷ 2 ? × 255 = 2 . 55 sec
? 1 ÷ 2 ? × 255 = 2 . 125 sec
DataSheet
VOLTAGE SAG DETECTION
The ADE7953 includes a sag detection feature that warns the
user when the absolute value of the line voltage falls below the
programmable threshold for a programmable number of line
cycles. This feature can provide an early warning signal that the
line voltage is dropping out. The voltage sag feature is controlled
by two registers: SAGCYC (Address 0x000) and SAGLVL
(Address 0x200 and Address 0x300). These registers control
the sag period and the sag voltage threshold, respectively.
Sag detection is disabled by default and can be enabled by
writing a nonzero value to both the SAGCYC and SAGLVL
registers. If either register is set to 0, the sag feature is disabled.
If a voltage sag condition occurs, the sag bit (Bit 19) in the
IRQSTATA register (Address 0x22D and Address 0x32D) and
in the RSTIRQSTATA register (Address 0x22E and Address
0x32E) is set to 1.
SETTING THE SAGCYC REGISTER
The 8-bit, unsigned SAGCYC register contains the program-
mable sag period. The sag period is the number of half line
cycles below which the voltage channel must remain before
a sag condition occurs. Each LSB of the SAGCYC register
corresponds to one half line cycle period. The SAGCYC
register holds a maximum value of 255.
At 50 Hz, the maximum sag cycle time is 2.55 seconds.
? 50 ?
At 60 Hz, the maximum sag cycle time is 2.125 seconds.
? 60 ?
ADE7953
If the SAGCYC value is modified after the feature is enabled,
the new SAGCYC period is effective immediately. Therefore, it
is possible for a sag event to be caused by a combination of sag
cycle periods. To prevent any overlap, the SAGLVL register
should be reset to 0 to effectively disable the feature before
the new cycle value is written to the SAGCYC register.
SETTING THE SAGLVL REGISTER
The 24-bit/32-bit SAGLVL register contains the amplitude that
the voltage channel must fall below before a sag event occurs.
Each LSB of this register maps exactly to the voltage channel
peak register; therefore, the amplitude can be set based on the
peak reading of the voltage channel. To set the SAGLVL register,
nominal voltage should be applied and a reading taken from the
RSTVPEAK register (Address 0x227 and Address 0x327) to reset
the peak level reading. After a wait period of a few line cycles,
the VPEAK register (Address 0x226 and Address 0x326) should
be read to determine the voltage input. This reading should
then be scaled to the amplitude required for sag detection.
For example, if a sag threshold of 80% of the nominal voltage is
required, the peak reading should be taken and a value of 80%
of this reading should be written to the SAGLVL register. This
method ensures that an accurate SAGLVL value is obtained for
the particular design.
VOLTAGE SAG INTERRUPT
The ADE7953 includes an interrupt that is associated with
the voltage sag detection feature. If this interrupt is enabled,
a voltage sag event causes the external IRQ pin to go low. This
interrupt is disabled by default and can be enabled by setting
the sag bit (Bit 19) in the IRQENA register (Address 0x22C
and Address 0x32C). See the ADE7953 Interrupts section.
Rev. B | Page 45 of 72
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