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| 型号： | ADE7953ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 48/72页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PH 28LFCSP |
| 标准包装： | 1 |
| 输入阻抗： | 660 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.4V |
| 电流 - 电源： | 6.8mA |
| 电源电压： | 3 V ~ 3.6 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 28-LFCSP-WQ（5x5） |
| 包装： | 托盘 |
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ADE7953
OVERCURRENT AND OVERVOLTAGE DETECTION
The ADE7953 provides an overcurrent and overvoltage feature
that detects whether the absolute value of the current or voltage
waveform exceeds a programmable threshold. This feature uses
the instantaneous voltage and current signals. The two registers
associated with this feature, OVLVL (Address 0x224 and
Address 0x324) and OILVL (Address 0x225 and Address 0x325),
are used to set the voltage and current channel thresholds, respec-
tively. The OILVL threshold register determines the threshold
for both the Current Channel A and Current Channel B over-
current features. The same threshold must therefore be used for
both Current Channel A and Current Channel B. The default
value of the OVLVL and OILVL registers is 0xFFFFFF, which
effectively disables the feature. Figure 66 shows the operation of
the overvoltage detection feature.
V
OVLVL
Data Sheet
As shown in Figure 67, if an overcurrent condition is detected
on Current Channel A, the OIA bit (Bit 13) of the IRQSTATA
register is set to 1. This bit can be cleared by reading from the
RSTIRQSTATA register. If an overcurrent condition is detected
on Current Channel B, the OIB bit (Bit 13) of the IRQSTATB
register (Address 0x230 and Address 0x330) is set to 1. This bit
can be cleared by reading from the RSTIRQSTATB register
(Address 0x231 and Address 0x331).
SETTING THE OVLVL AND OILVL REGISTERS
The 24-bit/32-bit unsigned OVLVL and OILVL registers map
directly to the VPEAK (Address 0x226 and Address 0x326)
and IAPEAK (Address 0x228 and Address 0x328) registers,
respectively (see the Peak Detection section). Note that after
gain calibration, Current Channel A and Current Channel B are
matched and, therefore, the IAPEAK and IBPEAK registers are
matched with common inputs. The settings of the OVLVL and
OILVL registers should be based on the VPEAK and IAPEAK
readings with full-scale inputs.
To set the OVLVL register, the maximum voltage input should
OV (BIT 16) OF
IRQSTATA REGISTER
OV RESET
LOW WHEN
RSTIRQSTATA
REGISTER
IS READ
be applied and a reading taken from the RSTVPEAK register
(Address 0x227 and Address 0x327). This resets the voltage peak
reading. After a wait period of a few line cycles, the VPEAK
register (Address 0x226 and Address 0x326) should be read to
Figure 66. Overvoltage Detection
As shown in Figure 66, if the ADE7953 detects an overvoltage
condition, the OV bit (Bit 16) of the IRQSTATA register
(Address 0x22D and Address 0x32D) is set to 1. This bit can be
cleared by reading the RSTIRQSTATA register (Address 0x22E
and Address 0x32E). The overcurrent detection feature works in
IA
OILVL
OIA RESET LOW
determine the voltage peak. This reading should then be scaled
to the amplitude required for overvoltage detection. For example,
if an overvoltage threshold of 120% of the maximum voltage is
required, the peak reading should be multiplied by 1.2 and the
resulting value written to the OVLVL register. This method ensures
that an accurate threshold is set for each individual design.
OVERVOLTAGE AND OVERCURRENT INTERRUPTS
Three interrupts are associated with the overvoltage and
overcurrent features. The first interrupt is associated with the
overvoltage feature; it is enabled by setting the OV bit (Bit 16)
of the IRQENA register (Address 0x22C and Address 0x32C).
When this bit is set, an overvoltage condition causes the
external IRQ pin to be pulled low.
A second interrupt is associated with the overcurrent detection
OIA (BIT 13) OF
IRQSTATA
REGISTER
IB
OILVL
OIB (BIT 13) OF
IRQSTATB
OIB RESET LOW
WHEN RSTIRQSTATB
REGISTER IS READ
WHEN RSTIRQSTATA
REGISTER IS READ
feature on Current Channel A. This interrupt is enabled by
setting the OIA bit (Bit 13) of the IRQENA register. When this
bit is set, an overcurrent condition on Current Channel A
causes the external IRQ pin to be pulled low.
The third interrupt is associated with the overcurrent detection
feature on Current Channel B. This interrupt is enabled by setting
the OIB bit (Bit 13) of the IRQENB register (Address 0x22F and
Address 0x32F). When this bit is set, an overcurrent condition
on Current Channel B causes the IRQ alternative output to be
triggered, if the alternative output is enabled (see the Current
REGISTER
Figure 67. Overcurrent Detection
Rev. B | Page 48 of 72
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