参数资料
| 型号： | ADM1067ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/32页 |
| 文件大小： | 0K |
| 描述： | IC SEQUENCER/SUPERVISOR 40-LFCSP |
| 标准包装： | 1 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 10 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
| 配用： | EVAL-ADM1067TQEBZ-ND - BOARD EVALUATION FOR ADM1067TQ |
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ADM1067
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 25 shows how the simple building block of a single
SE state can be used to build a power-up sequence for a three-
supply system. Table 8 lists the PDO outputs for each state in the
same SE implementation. In this system, a good 5 V supply on
VP1 and the VX1 pin held low are the triggers required to start
a power-up sequence. The sequence next turns on the 3.3 V supply,
then the 2.5 V supply (assuming successful turn-on of the 3.3 V
supply). When all three supplies have turned on correctly, the
PWRGD state is entered, where the SE remains until a fault occurs
on one of the three supplies or until it is instructed to go through
a power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on
a case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 25, the FSEL1
and FSEL2 states first identify which of the VP1, VP2, or VP3
pins has faulted, and then they take appropriate action.
SEQUENCE
STATES
IDLE1
VX1 = 0
IDLE2
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 25 to demonstrate
the actions of the state machine.
Sequence Detector
The sequence detector block is used to detect when a step in a
MONITOR FAULT
STATES
VP1 = 0
VP1 = 1
EN3V3
10ms
VP2 = 1
TIMEOUT
STATES
sequence has been completed. It looks for one of the SE inputs
to change state, and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
(VP1 + VP2) = 0
EN2V5
20ms
DIS3V3
VX1 = 1
block that is included in this detector can insert delays into a
VP3 = 1
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 24 is a block diagram of
the sequence detector.
(VP1 + VP2 + VP3) = 0
PWRGD
VP2 = 0
DIS2V5
VX1 = 1
VP1
VX5
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
SEQUENCE
DETECTOR
VP1 = 0
(VP1 +
VP2) = 0
FSEL2
FSEL1
VP3 = 0
VX1 = 1
TIMER
WARNINGS
INVERT
FORCE FLOW
(UNCONDITIONAL JUMP)
SELECT
Figure 24. Sequence Detector Block Diagram
Table 8. PDO Outputs for Each State
VP2 = 0
Figure 25. Sample Application Flow Diagram
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
0
0
0
IDLE2
0
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
Rev. D | Page 19 of 32
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相关代理商/技术参数 |
参数描述 |
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| ADM1067ACPZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Super Sequencer with Open-Loop Margining DACs |
| ADM1067ASU | 功能描述:IC SUPERVISOR/SEQUENCER 48-TQFP RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:Super Sequencer® 其它有关文件:STM6717 View All Specifications 标准包装:1 系列:- 类型:多压监控器 监视电压数目:2 输出:开路漏极或开路集电极 复位:低有效 复位超时:最小为 600 ms 电压 - 阀值:1.11V，3.075V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SC-74A，SOT-753 供应商设备封装:SOT-23-5 包装:Digi-Reel® 产品目录页面:1194 (CN2011-ZH PDF) 其它名称:497-7019-6 |
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| ADM1067ASU-REEL7 | 制造商:Analog Devices 功能描述:Sequencer 48-Pin TQFP T/R |
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